文件名称:MIPS
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用verilog编写的简单的类MIPS多周期流水化处理器实现，基本功能包括9条指令和两位动态分支预测，压缩包里的word详细说明了结构中的细节-Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies the details of the structure
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下载文件列表
计算机组成实验报告.docx
modelsim仿真代码\binary.txt
................\branchtb.txt
................\branch_table.v
................\DATA2.txt
................\EX.v
................\ID.v
................\ID.v.bak
................\IF.v
................\MEM.v
................\mips.v
................\mips_constant.v
................\mips_tb.v
................\reg_file.v
................\reg_stage.v
................\WB.v
modelsim仿真代码