文件名称:traffic-light
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设计任务：设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替运行。
设计要求：
1.要求黄灯先亮5秒，才能变换运行车道并且黄灯亮时另一干道的红灯按1Hz的频率闪烁。
2.要求通行时间及黄灯亮的时间均可在60秒内任意设定。
3.要求交通灯控制电路可以手动控制立即进入特殊运行状态，即两条道上红灯全亮，时钟停止计时。当特殊运行状态结束后，系统复原，继续正常运行。
-Design tasks: Design a crossroads of traffic light control circuit, requiring vehicle lanes and B. A two-lane road cross alternately run. Design requirements: 1. Require bright yellow first five seconds to change lanes and running a red light yellow light by the frequency of 1Hz other roads flashes. 2. Demands that the passage of time and the yellow light time can be set within 60 seconds. 3. Requests the traffic light control circuit can manually control immediately enter the special operation, that two trail-red light, the clock will stop the clock. After the end of the special operation status, system recovery, continue to operate normally.
设计要求：
1.要求黄灯先亮5秒，才能变换运行车道并且黄灯亮时另一干道的红灯按1Hz的频率闪烁。
2.要求通行时间及黄灯亮的时间均可在60秒内任意设定。
3.要求交通灯控制电路可以手动控制立即进入特殊运行状态，即两条道上红灯全亮，时钟停止计时。当特殊运行状态结束后，系统复原，继续正常运行。
-Design tasks: Design a crossroads of traffic light control circuit, requiring vehicle lanes and B. A two-lane road cross alternately run. Design requirements: 1. Require bright yellow first five seconds to change lanes and running a red light yellow light by the frequency of 1Hz other roads flashes. 2. Demands that the passage of time and the yellow light time can be set within 60 seconds. 3. Requests the traffic light control circuit can manually control immediately enter the special operation, that two trail-red light, the clock will stop the clock. After the end of the special operation status, system recovery, continue to operate normally.
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....\v3
....\..\Verilog1.asm.rpt
....\..\Verilog1.done
....\..\Verilog1.dpf
....\..\Verilog1.eda.rpt
....\..\Verilog1.fit.rpt
....\..\Verilog1.fit.summary
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....\..\Verilog1.map.smsg
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....\..\Verilog1.pin
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....\..\..\Verilog1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
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....\..\..\Verilog1.sta.rdb
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....\..\..\Verilog1.tiscmp.fast_1200mv_0c.ddb
....\..\..\Verilog1.tiscmp.slow_1200mv_0c.ddb
....\..\..\Verilog1.tiscmp.slow_1200mv_85c.ddb
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....\..\..\add_sub_unc.tdf
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....\..\..\wed.wsf