文件名称:digital_clk
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VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
digital_clk\db
...........\..\digital_clk.ace_cmp.bpm
...........\..\digital_clk.ace_cmp.cdb
...........\..\digital_clk.ace_cmp.hdb
...........\..\digital_clk.asm.qmsg
...........\..\digital_clk.asm.rdb
...........\..\digital_clk.asm_labs.ddb
...........\..\digital_clk.cbx.xml
...........\..\digital_clk.cmp.bpm
...........\..\digital_clk.cmp.cdb
...........\..\digital_clk.cmp.hdb
...........\..\digital_clk.cmp.idb
...........\..\digital_clk.cmp.kpt
...........\..\digital_clk.cmp.logdb
...........\..\digital_clk.cmp.rdb
...........\..\digital_clk.cmp_merge.kpt
...........\..\digital_clk.cmp0.ddb
...........\..\digital_clk.cmp1.ddb
...........\..\digital_clk.db_info
...........\..\digital_clk.eco.cdb
...........\..\digital_clk.eda.qmsg
...........\..\digital_clk.fit.qmsg
...........\..\digital_clk.hier_info
...........\..\digital_clk.hif
...........\..\digital_clk.ipinfo
...........\..\digital_clk.lpc.html
...........\..\digital_clk.lpc.rdb
...........\..\digital_clk.lpc.txt
...........\..\digital_clk.map.ammdb
...........\..\digital_clk.map.bpm
...........\..\digital_clk.map.cdb
...........\..\digital_clk.map.hdb
...........\..\digital_clk.map.kpt
...........\..\digital_clk.map.logdb
...........\..\digital_clk.map.qmsg
...........\..\digital_clk.map.rdb
...........\..\digital_clk.map_bb.cdb
...........\..\digital_clk.map_bb.hdb
...........\..\digital_clk.map_bb.logdb
...........\..\digital_clk.pplq.rdb
...........\..\digital_clk.pre_map.hdb
...........\..\digital_clk.pti_db_list.ddb
...........\..\digital_clk.root_partition.map.reg_db.cdb
...........\..\digital_clk.routing.rdb
...........\..\digital_clk.rtlv.hdb
...........\..\digital_clk.rtlv_sg.cdb
...........\..\digital_clk.rtlv_sg_swap.cdb
...........\..\digital_clk.sgdiff.cdb
...........\..\digital_clk.sgdiff.hdb
...........\..\digital_clk.sld_design_entry.sci
...........\..\digital_clk.sld_design_entry_dsc.sci
...........\..\digital_clk.smart_action.txt
...........\..\digital_clk.smp_dump.txt
...........\..\digital_clk.sta.qmsg
...........\..\digital_clk.sta.rdb
...........\..\digital_clk.sta_cmp.6_slow.tdb
...........\..\digital_clk.syn_hier_info
...........\..\digital_clk.tis_db_list.ddb
...........\..\digital_clk.tmw_info
...........\..\digital_clk.vpr.ammdb
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_digital_clk.qmsg
...........\digital_clk.qpf
...........\digital_clk.qsf
...........\digital_clk.qws
...........\digital_clk.vhd
...........\digital_clk.vhd.bak
...........\incremental_db
...........\..............\compiled_partitions
...........\..............\...................\digital_clk.db_info
...........\..............\...................\digital_clk.root_partition.cmp.ammdb
...........\..............\...................\digital_clk.root_partition.cmp.cdb
...........\..............\...................\digital_clk.root_partition.cmp.dfp
...........\..............\...................\digital_clk.root_partition.cmp.hdb
...........\..............\...................\digital_clk.root_partition.cmp.kpt
...........\..............\...................\digital_clk.root_partition.cmp.logdb
...........\..............\...................\digital_clk.root_partition.cmp.rcfdb
...........\..............\...................\digital_clk.root_partition.map.cdb
...........\..............\...................\digital_clk.root_partition.map.dpi
...........\..............\...................\digital_clk.root_partition.map.hbdb.cdb
...........\..............\...................\digital_clk.root_partition.map.hbdb.hb_info
...........\..............\...................\digital_clk.root_partition.map.hbdb.hdb
...........\..............\...................\digital_clk.root_partition.map.hbdb.sig
...........\..............\...................\digital_clk.root_partition.map.hdb
...........\..............\...................\digital_clk.root_partition.map.kpt
...........\..............\README
...........\output_files
...........\............\digital_clk.asm.rpt
...........\............\digital_clk.cdf
...........\............\digital_clk.done
...........\...........