文件名称:CPU
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我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan University. This is an 8-bit CPU design VHDL implementation. The CPU based on RISC architecture to achieve the basic functions, such as cpu: arithmetic operations, jumps and so on. In addition, there are a ROM area 17, is stored in the instruction. You can write some 17 of the instruction code, and placed in the ROM area, the CPU will automatically run the result. Compression bag is the source code and design requirements of our time. When the final commissioning source code is placed in the address 0 17 of Fibonacci numbers (Fibonacci Numbers) instruction. You can see the results of the simulation by modelsim.
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下载文件列表
CPU\CPU Title.pdf
...\cpu
...\...\ALU.vhd
...\...\ALU_tb.vhd
...\...\IDU.vhd
...\...\IDU_tb.vhd
...\...\inst_ROM.vhd
...\...\inst_ROM_tb.vhd
...\...\MicroController.vhd
...\...\MicroController_sources.f
...\...\MicroController_tb.vhd
...\...\Register_Bank.vhd
...\...\Register_Bank_tb.vhd