文件名称:six_wave
介绍说明－－下载内容均来自于网络，请自行研究使用
产生六种波形的DDS信号发生器，用verilog实现，有modersim仿真程序和结果，产生正玄波，方波，锯齿波，三角波，阶梯波。实现完全可用-the dds can output six signal，write in verilog。
(系统自动生成,下载前可以参看下载内容)
下载文件列表
six_wave\db\altsyncram_1t81.tdf
........\..\altsyncram_bs81.tdf
........\..\altsyncram_fs81.tdf
........\..\altsyncram_jv81.tdf
........\..\altsyncram_ps81.tdf
........\..\altsyncram_rs81.tdf
........\..\logic_util_heursitic.dat
........\..\prev_cmp_TOP.qmsg
........\..\TOP.cbx.xml
........\..\TOP.cmp.rdb
........\..\TOP.cmp_merge.kpt
........\..\TOP.db_info
........\..\TOP.eda.qmsg
........\..\TOP.hier_info
........\..\TOP.hif
........\..\TOP.lpc.html
........\..\TOP.lpc.rdb
........\..\TOP.lpc.txt
........\..\TOP.map.bpm
........\..\TOP.map.cdb
........\..\TOP.map.hdb
........\..\TOP.map.kpt
........\..\TOP.map.logdb
........\..\TOP.map.qmsg
........\..\TOP.map_bb.cdb
........\..\TOP.map_bb.hdb
........\..\TOP.map_bb.logdb
........\..\TOP.pre_map.cdb
........\..\TOP.pre_map.hdb
........\..\TOP.root_partition.map.reg_db.cdb
........\..\TOP.rpp.qmsg
........\..\TOP.rtlv.hdb
........\..\TOP.rtlv_sg.cdb
........\..\TOP.rtlv_sg_swap.cdb
........\..\TOP.sgate.rvd
........\..\TOP.sgate_sm.rvd
........\..\TOP.sgdiff.cdb
........\..\TOP.sgdiff.hdb
........\..\TOP.sld_design_entry.sci
........\..\TOP.sld_design_entry_dsc.sci
........\..\TOP.smart_action.txt
........\..\TOP.syn_hier_info
........\..\TOP.tis_db_list.ddb
........\..\TOP.tmw_info
........\Div_clk.v
........\Div_clk.v.bak
........\fang.mif
........\greybox_tmp\cbx_args.txt
........\incremental_db\compiled_partitions\TOP.db_info
........\..............\...................\TOP.root_partition.map.cdb
........\..............\...................\TOP.root_partition.map.dpi
........\..............\...................\TOP.root_partition.map.hbdb.cdb
........\..............\...................\TOP.root_partition.map.hbdb.hb_info
........\..............\...................\TOP.root_partition.map.hbdb.hdb
........\..............\...................\TOP.root_partition.map.hbdb.sig
........\..............\...................\TOP.root_partition.map.hdb
........\..............\...................\TOP.root_partition.map.kpt
........\..............\README
........\jia.mif
........\jie.mif
........\Key_debuce.v
........\Key_debuce.v.bak
........\min.mif
........\rom_fang.qip
........\rom_fang.v
........\rom_fang_bb.v
........\rom_jia.qip
........\rom_jia.v
........\rom_jia_bb.v
........\rom_jie.qip
........\rom_jie.v
........\rom_jie_bb.v
........\rom_min.qip
........\rom_min.v
........\rom_min_bb.v
........\rom_san.qip
........\rom_san.v
........\rom_san_bb.v
........\rom_sin.qip
........\rom_sin.v
........\rom_sin_bb.v
........\san.mif
........\.imulation\modelsim\fang.mif
........\..........\........\fang.ver
........\..........\........\jia.mif
........\..........\........\jia.ver
........\..........\........\jie.mif
........\..........\........\jie.ver
........\..........\........\min.mif
........\..........\........\min.ver
........\..........\........\modelsim.ini
........\..........\........\msim_transcript
........\..........\........\rtl_work\@div_clk\verilog.prw
........\..........\........\........\........\verilog.psm
........\..........\........\........\........\_primary.dat
........\..........\........\........\........\_primary.dbs
........\..........\........\........\........\_primary.vhd
........\..........\........\........\.key_debuce\verilog.prw
........\..........\........\........\...........\verilog.psm
........\..........\........\........\...........\_primary.dat