文件名称:taxi_THE-FINAL
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基于FPGA的汽车计费系统，根据不同的情况会有不同的计费方式，基本能够符合实际情况-FPGA-based auto billing system, depending on the situation will be different billing methods, and can basically meet the actual situation
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下载文件列表
taxi_THE FINAL
..............\.lso
..............\.Xil
..............\decoder24.cmd_log
..............\decoder24.prj
..............\decoder24.spl
..............\decoder24.stx
..............\decoder24.sym
..............\decoder24.vhd
..............\decoder24.xst
..............\decoder24_vhdl.prj
..............\di.cmd_log
..............\di.prj
..............\di.spl
..............\di.stx
..............\di.sym
..............\di.vhd
..............\di.xst
..............\di_vhdl.prj
..............\fenpin.cmd_log
..............\fenpin.prj
..............\fenpin.spl
..............\fenpin.stx
..............\fenpin.sym
..............\fenpin.vhd
..............\fenpin.xst
..............\fenpin_vhdl.prj
..............\impact.xsl
..............\impact_impact.xwbt
..............\ipcore_dir
..............\iseconfig
..............\.........\jifei.xreport
..............\.........\taxi.projectmgr
..............\.........\top.xreport
..............\jifei.cmd_log
..............\jifei.prj
..............\jifei.spl
..............\jifei.stx
..............\jifei.sym
..............\jifei.vhd
..............\jifei.xst
..............\jifei_summary.html
..............\jifei_vhdl.prj
..............\netgen
..............\......\synthesis
..............\......\.........\top_synthesis.nlf
..............\......\.........\top_synthesis.vhd
..............\pa.fromNetlist.tcl
..............\pepExtractor.prj
..............\planAhead.ngc2edif.log
..............\planAhead_pid1504.debug
..............\planAhead_run_1
..............\...............\planAhead.jou
..............\...............\planAhead.log
..............\...............\planAhead_run.log
..............\...............\taxi.data
..............\...............\.........\cache
..............\...............\.........\.....\top_ngc_zx.edif
..............\...............\.........\constrs_1
..............\...............\.........\.........\designprops.xml
..............\...............\.........\.........\fileset.xml
..............\...............\.........\.........\usercols.xml
..............\...............\.........\runs
..............\...............\.........\....\impl_1.psg
..............\...............\.........\....\runs.xml
..............\...............\.........\sim_1
..............\...............\.........\.....\fileset.xml
..............\...............\.........\sources_1
..............\...............\.........\.........\chipscope.xml
..............\...............\.........\.........\fileset.xml
..............\...............\.........\.........\ports.xml
..............\...............\.........\wt
..............\...............\.........\..\java_command_handlers.wdf
..............\...............\.........\..\project.wpc
..............\...............\.........\..\webtalk_pa.xml
..............\...............\taxi.ppr
..............\sch2HdlBatchFile
..............\se.cmd_log
..............\se.prj
..............\se.spl
..............\se.stx
..............\se.sym
..............\se.vhd
..............\se.xst
..............\se_vhdl.prj
..............\taxi.gise
..............\taxi.xise
..............\top.bgn
..............\top.bit
..............\top.bld
..............\top.cmd_log
..............\top.drc
..............\top.jhd
..............\top.lso
..............\top.ncd
..............\top.ngc
..............\top.ngd
..............\top.ngr
..............\top.pad
..............\top.par