文件名称:flow_proc
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA FLOW verilog流水线把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。以芯片面积换取时间，即面积换取频率-FPGA FLOW verilog To a complex pipeline logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal, increasing the frequency. The chip area for time, that area in exchange for frequency
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下载文件列表
flow_proc
.........\db
.........\..\flow_proc.cbx.xml
.........\..\flow_proc.cmp.rdb
.........\..\flow_proc.cmp_merge.kpt
.........\..\flow_proc.db_info
.........\..\flow_proc.hier_info
.........\..\flow_proc.hif
.........\..\flow_proc.lpc.html
.........\..\flow_proc.lpc.rdb
.........\..\flow_proc.lpc.txt
.........\..\flow_proc.map.bpm
.........\..\flow_proc.map.cdb
.........\..\flow_proc.map.hdb
.........\..\flow_proc.map.kpt
.........\..\flow_proc.map.logdb
.........\..\flow_proc.map.qmsg
.........\..\flow_proc.map_bb.cdb
.........\..\flow_proc.map_bb.hdb
.........\..\flow_proc.map_bb.logdb
.........\..\flow_proc.pre_map.cdb
.........\..\flow_proc.pre_map.hdb
.........\..\flow_proc.rtlv.hdb
.........\..\flow_proc.rtlv_sg.cdb
.........\..\flow_proc.rtlv_sg_swap.cdb
.........\..\flow_proc.sgdiff.cdb
.........\..\flow_proc.sgdiff.hdb
.........\..\flow_proc.sld_design_entry.sci
.........\..\flow_proc.sld_design_entry_dsc.sci
.........\..\flow_proc.smart_action.txt
.........\..\flow_proc.syn_hier_info
.........\..\flow_proc.tis_db_list.ddb
.........\..\logic_util_heursitic.dat
.........\..\prev_cmp_flow_proc.map.qmsg
.........\..\prev_cmp_flow_proc.qmsg
.........\flow_proc.done
.........\flow_proc.flow.rpt
.........\flow_proc.map.rpt
.........\flow_proc.map.summary
.........\flow_proc.qpf
.........\flow_proc.qpf.bak
.........\flow_proc.qsf
.........\flow_proc.qsf.bak
.........\flow_proc.qws
.........\flow_proc_assignment_defaults.qdf
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\...................\flow_proc.db_info
.........\..............\...................\flow_proc.root_partition.map.cdb
.........\..............\...................\flow_proc.root_partition.map.dpi
.........\..............\...................\flow_proc.root_partition.map.hbdb.cdb
.........\..............\...................\flow_proc.root_partition.map.hbdb.hb_info
.........\..............\...................\flow_proc.root_partition.map.hbdb.hdb
.........\..............\...................\flow_proc.root_partition.map.hbdb.sig
.........\..............\...................\flow_proc.root_partition.map.hdb
.........\..............\...................\flow_proc.root_partition.map.kpt
.........\..............\README
.........\RTL
.........\...\flow_proc.jpg
.........\...\flow_proc.v
.........\...\flow_proc.v.bak
.........\...\xxxx.v.bak
.........\TB
.........\..\flow_proc.v
.........\..\flow_proc.v.bak
.........\..\TB.cr.mti
.........\..\TB.mpf
.........\..\TB.v
.........\..\TB.v.bak
.........\..\transcript
.........\..\vsim.wlf
.........\..\wave.do
.........\..\work
.........\..\....\@t@b
.........\..\....\....\verilog.asm
.........\..\....\....\_primary.dat
.........\..\....\....\_primary.vhd
.........\..\....\flow_proc
.........\..\....\.........\verilog.asm
.........\..\....\.........\_primary.dat
.........\..\....\.........\_primary.vhd
.........\..\....\TB
.........\..\....\..\verilog.asm
.........\..\....\..\_primary.dat
.........\..\....\..\_primary.vhd
.........\..\....\_info
.........\详细设计方案
.........\............\~$设计方案_流水处理.doc