文件名称:vhdl-bjq

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2014-12-31
  • 文件大小:
  • 230kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 秦**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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用vhdl语言编写表决器程序,通过代码实现来实现,采用三种实现方式。-Voting procedures used to write vhdl language code
(系统自动生成,下载前可以参看下载内容)

下载文件列表





vhdl 韩梦芯\homework1\assignment_defaults.qdf

...........\.........\db\prev_cmp_V01.asm.qmsg

...........\.........\..\prev_cmp_V01.eda.qmsg

...........\.........\..\prev_cmp_V01.fit.qmsg

...........\.........\..\prev_cmp_V01.map.qmsg

...........\.........\..\prev_cmp_V01.qmsg

...........\.........\..\prev_cmp_V01.tan.qmsg

...........\.........\..\V01.asm.qmsg

...........\.........\..\V01.cbx.xml

...........\.........\..\V01.cmp.bpm

...........\.........\..\V01.cmp.cdb

...........\.........\..\V01.cmp.ecobp

...........\.........\..\V01.cmp.hdb

...........\.........\..\V01.cmp.logdb

...........\.........\..\V01.cmp.rdb

...........\.........\..\V01.cmp.tdb

...........\.........\..\V01.cmp0.ddb

...........\.........\..\V01.cmp2.ddb

...........\.........\..\V01.db_info

...........\.........\..\V01.eco.cdb

...........\.........\..\V01.eda.qmsg

...........\.........\..\V01.fit.qmsg

...........\.........\..\V01.hier_info

...........\.........\..\V01.hif

...........\.........\..\V01.map.bpm

...........\.........\..\V01.map.cdb

...........\.........\..\V01.map.ecobp

...........\.........\..\V01.map.hdb

...........\.........\..\V01.map.logdb

...........\.........\..\V01.map.qmsg

...........\.........\..\V01.map_bb.cdb

...........\.........\..\V01.map_bb.hdb

...........\.........\..\V01.map_bb.hdbx

...........\.........\..\V01.map_bb.logdb

...........\.........\..\V01.pre_map.cdb

...........\.........\..\V01.pre_map.hdb

...........\.........\..\V01.psp

...........\.........\..\V01.root_partition.cmp.atm

...........\.........\..\V01.root_partition.cmp.dfp

...........\.........\..\V01.root_partition.cmp.hdbx

...........\.........\..\V01.root_partition.cmp.logdb

...........\.........\..\V01.root_partition.cmp.rcf

...........\.........\..\V01.root_partition.map.atm

...........\.........\..\V01.root_partition.map.hdbx

...........\.........\..\V01.root_partition.map.info

...........\.........\..\V01.rtlv.hdb

...........\.........\..\V01.rtlv_sg.cdb

...........\.........\..\V01.rtlv_sg_swap.cdb

...........\.........\..\V01.sgdiff.cdb

...........\.........\..\V01.sgdiff.hdb

...........\.........\..\V01.signalprobe.cdb

...........\.........\..\V01.sld_design_entry.sci

...........\.........\..\V01.sld_design_entry_dsc.sci

...........\.........\..\V01.syn_hier_info

...........\.........\..\V01.tan.qmsg

...........\.........\..\V01.tis_db_list.ddb

...........\.........\..\V01.tmw_info

...........\.........\output_files\V01.asm.rpt

...........\.........\............\V01.done

...........\.........\............\V01.eda.rpt

...........\.........\............\V01.fit.rpt

...........\.........\............\V01.fit.smsg

...........\.........\............\V01.fit.summary

...........\.........\............\V01.flow.rpt

...........\.........\............\V01.jdi

...........\.........\............\V01.map.rpt

...........\.........\............\V01.map.summary

...........\.........\............\V01.pin

...........\.........\............\V01.pof

...........\.........\............\V01.sof

...........\.........\............\V01.sta.rpt

...........\.........\............\V01.sta.summary

...........\.........\............\V01.tan.rpt

...........\.........\............\V01.tan.summary

...........\.........\simulation\modelsim\V01.sft

...........\.........\..........\........\V01.vho

...........\.........\..........\........\V01_modelsim.xrf

...........\.........\..........\........\V01_vhd.sdo

...........\.........\V01.cbx.xml

...........\.........\V01.qpf

...........\.........\V01.qsf

...........\.........\V01.qws

...........\.........\V01.vhd

...........\.........\V01_nativelink_simulation.rpt

...........\.........\V01_tmp_archive.qarlog

...........\.........\simulation\modelsim

...........\.........\db

...........\.........\output_files

...........\.........\simulation

...........\homework1

vhdl 韩梦芯

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