文件名称:ck1
介绍说明－－下载内容均来自于网络，请自行研究使用
用FPGA实现的数码管时钟，使用的是Nexys4开发板，所以使用了视觉暂留原理实现数码管的显示。-FPGA implementation with digital clock, using Nexys4 development board, so the use of the principle of persistence of vision to realize digital tube display.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ck1\ck.cache\wt\java_command_handlers.wdf
...\........\..\synthesis.wdf
...\........\..\webtalk_pa.xml
...\........\..\xsim.wdf
...\...ioplanning\constrs_1\designprops.xml
...\.............\.........\usercols.xml
...\...runs\.jobs\vrs_config_1.xml
...\.......\.....\vrs_config_2.xml
...\.......\.....\vrs_config_3.xml
...\.......\.....\vrs_config_4.xml
...\.......\.....\vrs_config_5.xml
...\.......\.....\vrs_config_6.xml
...\.......\impl_1\.init_design.begin.rst
...\.......\......\.init_design.end.rst
...\.......\......\.opt_design.begin.rst
...\.......\......\.opt_design.end.rst
...\.......\......\.place_design.begin.rst
...\.......\......\.place_design.end.rst
...\.......\......\.route_design.begin.rst
...\.......\......\.route_design.end.rst
...\.......\......\.Vivado Implementation.queue.rst
...\.......\......\.vivado.begin.rst
...\.......\......\.vivado.end.rst
...\.......\......\.write_bitstream.begin.rst
...\.......\......\.write_bitstream.end.rst
...\.......\......\clock.bit
...\.......\......\clock.tcl
...\.......\......\clock.vdi
...\.......\......\clock_clock_utilization_placed.rpt
...\.......\......\clock_control_sets_placed.rpt
...\.......\......\clock_drc_routed.pb
...\.......\......\clock_drc_routed.rpt
...\.......\......\clock_io_placed.rpt
...\.......\......\clock_opt.dcp
...\.......\......\clock_placed.dcp
...\.......\......\clock_power_routed.rpt
...\.......\......\clock_power_summary_routed.pb
...\.......\......\clock_routed.dcp
...\.......\......\clock_route_status.pb
...\.......\......\clock_route_status.rpt
...\.......\......\clock_timing_summary_routed.pb
...\.......\......\clock_timing_summary_routed.rpt
...\.......\......\clock_utilization_placed.pb
...\.......\......\clock_utilization_placed.rpt
...\.......\......\gen_run.xml
...\.......\......\htr.txt
...\.......\......\init_design.pb
...\.......\......\ISEWrap.js
...\.......\......\ISEWrap.sh
...\.......\......\opt_design.pb
...\.......\......\place_design.pb
...\.......\......\project.wdf
...\.......\......\route_design.pb
...\.......\......\rundef.js
...\.......\......\runme.bat
...\.......\......\runme.log
...\.......\......\runme.sh
...\.......\......\usage_statistics_webtalk.html
...\.......\......\usage_statistics_webtalk.xml
...\.......\......\vivado.jou
...\.......\......\vivado.pb
...\.......\......\write_bitstream.pb
...\.......\synth_1\.Vivado Synthesis.queue.rst
...\.......\.......\.vivado.begin.rst
...\.......\.......\.vivado.end.rst
...\.......\.......\clock.dcp
...\.......\.......\clock.tcl
...\.......\.......\clock.vds
...\.......\.......\clock_utilization_synth.pb
...\.......\.......\clock_utilization_synth.rpt
...\.......\.......\gen_run.xml
...\.......\.......\htr.txt
...\.......\.......\ISEWrap.js
...\.......\.......\ISEWrap.sh
...\.......\.......\rundef.js
...\.......\.......\runme.bat
...\.......\.......\runme.log
...\.......\.......\runme.sh
...\.......\.......\vivado.jou
...\.......\.......\vivado.pb
...\...sim\sim_1\behav\compile.bat
...\......\.....\.....\compile.sh
...\......\.....\.....\test_ck.prj
...\......\.....\.....\test_ck.tcl
...\......\.....\.....\test_ck_behav.log
...\......\.....\.....\test_ck_behav.wdb
...\......\.....\.....\xelab.log
...\......\.....\.....\xelab.pb
...\......\.....\.....\.sim.dir\test_ck_behav\Compile_Options.txt
...\......\.....\.....\........\.............\xsim.dbg
...\......\.....\.....\........\.............\xsim.mem
...\......\.....\.....\........\.............\xsim.reloc
...\......\.....\.....\........\.............\xsim.rtti
...\......\.....\.....\........\.............\xsim.svtype
...\......\.....\.....\........\.............\xsim.type
...\......\.....\.....\........\.............\xsim.xdbg
...\......\.....\.....\........\.............\xsimcrash.log
...\......\.....\.....\........\.............\xsimk.exe
...\......\.....\.....\........\.............\xsimkernel.log
...\......\.....\.....\........\xil_defaultlib\clock.sdb