文件名称:spi_verilog
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在SPI操作中，最重要的两项设置就是时钟极性（CPOL或UCCKPL）和时钟相位（CPHA或UCCKPH）。时钟极性设置时钟空闲时的电平，时钟相位设置读取数据和发送数据的时钟沿。
主机和从机的发送数据是同时完成的，两者的接收数据也是同时完成的。所以为了保证主从机正确通信，应使得它们的SPI具有相同的时钟极性和时钟相位。
-In more details:
1. The master pulls SSEL down to indicate to the slave that communication is starting (SSEL is active low).
2. The master toggles the clock eight times and sends eight data bits on its MOSI line. At the same time it receives eight data bits the slave on the MISO line.
3. The master pulls SSEL up to indicate that the transfer is over.
主机和从机的发送数据是同时完成的，两者的接收数据也是同时完成的。所以为了保证主从机正确通信，应使得它们的SPI具有相同的时钟极性和时钟相位。
-In more details:
1. The master pulls SSEL down to indicate to the slave that communication is starting (SSEL is active low).
2. The master toggles the clock eight times and sends eight data bits on its MOSI line. At the same time it receives eight data bits the slave on the MISO line.
3. The master pulls SSEL up to indicate that the transfer is over.
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下载文件列表
verilog\spi_clgen.v
.......\spi_defines.v
.......\spi_shift.v
.......\spi_top.v
.......\timescale.v
verilog