文件名称:uart_yll_pro
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基于CPLD的 I2C通信，模块化设计，已在示波器上验证-CPLD The I2C communication, based on a modular design, verified on an oscilloscope
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下载文件列表
uart_yll_pro\bbff.v
............\bbff.v.bak
............\db\prev_cmp_uart_yll.asm.qmsg
............\..\prev_cmp_uart_yll.eda.qmsg
............\..\prev_cmp_uart_yll.fit.qmsg
............\..\prev_cmp_uart_yll.map.qmsg
............\..\prev_cmp_uart_yll.qmsg
............\..\prev_cmp_uart_yll.sim.qmsg
............\..\prev_cmp_uart_yll.tan.qmsg
............\..\uart_yll.asm.qmsg
............\..\uart_yll.asm_labs.ddb
............\..\uart_yll.atom_map.rvd
............\..\uart_yll.cbx.xml
............\..\uart_yll.cmp.cdb
............\..\uart_yll.cmp.hdb
............\..\uart_yll.cmp.logdb
............\..\uart_yll.cmp.rdb
............\..\uart_yll.cmp.tdb
............\..\uart_yll.cmp0.ddb
............\..\uart_yll.db_info
............\..\uart_yll.eco.cdb
............\..\uart_yll.eda.qmsg
............\..\uart_yll.eds_overflow
............\..\uart_yll.fit.qmsg
............\..\uart_yll.hier_info
............\..\uart_yll.hif
............\..\uart_yll.map.cdb
............\..\uart_yll.map.hdb
............\..\uart_yll.map.logdb
............\..\uart_yll.map.qmsg
............\..\uart_yll.pre_map.cdb
............\..\uart_yll.pre_map.hdb
............\..\uart_yll.rpp.qmsg
............\..\uart_yll.rtlv.hdb
............\..\uart_yll.rtlv_sg.cdb
............\..\uart_yll.rtlv_sg_swap.cdb
............\..\uart_yll.sgate.rvd
............\..\uart_yll.sgate_sm.rvd
............\..\uart_yll.sgdiff.cdb
............\..\uart_yll.sgdiff.hdb
............\..\uart_yll.signalprobe.cdb
............\..\uart_yll.sim.cvwf
............\..\uart_yll.sim.hdb
............\..\uart_yll.sim.qmsg
............\..\uart_yll.sim.rdb
............\..\uart_yll.sld_design_entry.sci
............\..\uart_yll.sld_design_entry_dsc.sci
............\..\uart_yll.syn_hier_info
............\..\uart_yll.tan.qmsg
............\..\uart_yll.tis_db_list.ddb
............\..\uart_yll.tmw_info
............\..\wed.wsf
............\rcv.bsf
............\rcv.v
............\rcv.v.bak
............\rcv.vPreview
............\Set_Baud.bsf
............\Set_Baud.v
............\Set_Baud.v.bak
............\simulation\modelsim\uart_yll.sft
............\..........\........\uart_yll.vo
............\..........\........\uart_yll_modelsim.xrf
............\..........\........\uart_yll_v.sdo
............\timing\primetime\uart_yll.vo
............\......\.........\uart_yll_pt_v.tcl
............\......\.........\uart_yll_v.sdo
............\txd.bsf
............\TXD.v
............\TXD.v.bak
............\txd2.bsf
............\txd2.v
............\txd2.v.bak
............\txdd.bsf
............\uart.v
............\uart_yll.asm.rpt
............\uart_yll.bdf
............\uart_yll.cdf
............\uart_yll.done
............\uart_yll.dpf
............\uart_yll.eda.rpt
............\uart_yll.fit.rpt
............\uart_yll.fit.smsg
............\uart_yll.fit.summary
............\uart_yll.flow.rpt
............\uart_yll.map.rpt
............\uart_yll.map.smsg
............\uart_yll.map.summary
............\uart_yll.pin
............\uart_yll.pof
............\uart_yll.qpf
............\uart_yll.qsf
............\uart_yll.qws
............\uart_yll.sim.rpt
............\uart_yll.tan.rpt
............\uart_yll.tan.summary
............\uart_yll.vwf
............\Verilog1.v
............\Verilog2.v
............\Verilog2.v.bak
............\simulation\modelsim