文件名称:04_div_clk_1Hz

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [HTML]
  • 上传时间:
  • 2015-11-08
  • 文件大小:
  • 3.1mb
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  • 0次
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  • 刘*
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verilog HDL 描述分频电路 产生1Hz脉冲方波信号 系统时钟频率50MHz-this is a divide circuit module to get a plus signal of 1Hz
(系统自动生成,下载前可以参看下载内容)

下载文件列表





04_div_clk_1Hz

..............\quartus

..............\.......\db

..............\.......\..\.cmp.kpt

..............\.......\..\div_clk.amm.cdb

..............\.......\..\div_clk.asm.qmsg

..............\.......\..\div_clk.asm.rdb

..............\.......\..\div_clk.asm_labs.ddb

..............\.......\..\div_clk.cbx.xml

..............\.......\..\div_clk.cmp.bpm

..............\.......\..\div_clk.cmp.cdb

..............\.......\..\div_clk.cmp.hdb

..............\.......\..\div_clk.cmp.kpt

..............\.......\..\div_clk.cmp.logdb

..............\.......\..\div_clk.cmp.rdb

..............\.......\..\div_clk.cmp_merge.kpt

..............\.......\..\div_clk.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

..............\.......\..\div_clk.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd

..............\.......\..\div_clk.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd

..............\.......\..\div_clk.db_info

..............\.......\..\div_clk.eda.qmsg

..............\.......\..\div_clk.fit.qmsg

..............\.......\..\div_clk.hier_info

..............\.......\..\div_clk.hif

..............\.......\..\div_clk.idb.cdb

..............\.......\..\div_clk.lpc.html

..............\.......\..\div_clk.lpc.rdb

..............\.......\..\div_clk.lpc.txt

..............\.......\..\div_clk.map.bpm

..............\.......\..\div_clk.map.cdb

..............\.......\..\div_clk.map.hdb

..............\.......\..\div_clk.map.kpt

..............\.......\..\div_clk.map.logdb

..............\.......\..\div_clk.map.qmsg

..............\.......\..\div_clk.map.rdb

..............\.......\..\div_clk.map_bb.cdb

..............\.......\..\div_clk.map_bb.hdb

..............\.......\..\div_clk.map_bb.logdb

..............\.......\..\div_clk.pre_map.cdb

..............\.......\..\div_clk.pre_map.hdb

..............\.......\..\div_clk.root_partition.map.reg_db.cdb

..............\.......\..\div_clk.routing.rdb

..............\.......\..\div_clk.rtlv.hdb

..............\.......\..\div_clk.rtlv_sg.cdb

..............\.......\..\div_clk.rtlv_sg_swap.cdb

..............\.......\..\div_clk.sgdiff.cdb

..............\.......\..\div_clk.sgdiff.hdb

..............\.......\..\div_clk.sld_design_entry.sci

..............\.......\..\div_clk.sld_design_entry_dsc.sci

..............\.......\..\div_clk.smart_action.txt

..............\.......\..\div_clk.sta.qmsg

..............\.......\..\div_clk.sta.rdb

..............\.......\..\div_clk.sta_cmp.8_slow_1200mv_85c.tdb

..............\.......\..\div_clk.syn_hier_info

..............\.......\..\div_clk.tis_db_list.ddb

..............\.......\..\div_clk.tiscmp.fast_1200mv_0c.ddb

..............\.......\..\div_clk.tiscmp.fastest_slow_1200mv_0c.ddb

..............\.......\..\div_clk.tiscmp.fastest_slow_1200mv_85c.ddb

..............\.......\..\div_clk.tiscmp.slow_1200mv_0c.ddb

..............\.......\..\div_clk.tiscmp.slow_1200mv_85c.ddb

..............\.......\..\div_clk.tmw_info

..............\.......\..\logic_util_heursitic.dat

..............\.......\..\prev_cmp_div_clk.qmsg

..............\.......\div_clk.asm.rpt

..............\.......\div_clk.bsf

..............\.......\div_clk.cdf

..............\.......\div_clk.done

..............\.......\div_clk.eda.rpt

..............\.......\div_clk.fit.rpt

..............\.......\div_clk.fit.smsg

..............\.......\div_clk.fit.summary

..............\.......\div_clk.flow.rpt

..............\.......\div_clk.jdi

..............\.......\div_clk.map.rpt

..............\.......\div_clk.map.summary

..............\.......\div_clk.pin

..............\.......\div_clk.pof

..............\.......\div_clk.qpf

..............\.......\div_clk.qsf

..............\.......\div_clk.qws

..............\.......\div_clk.sld

..............\.......\div_clk.sof

..............\.......\div_clk.sta.rpt

..............\.......\div_clk.sta.summary

..............\.......\div_clk_assignment_defaults.qdf

..............\.......\div_clk_nativelink_simulation.rpt

..............\.......\incremental_db

..............\.......\..............\README

..............\.......\..............\compiled_partitions

..............\.......\..............\...................\d

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