文件名称:1602-display-char
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这是lcd1602的显示字符的Verilog源代码，经过测试可用，便于读者学习。-This is the LCD1602 of the Verilog source code, after testing can be used to facilitate the reader to learn.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
1602 display char\db
.................\..\add_sub_lkc.tdf
.................\..\add_sub_mkc.tdf
.................\..\alt_u_div_ive.tdf
.................\..\alt_u_div_kve.tdf
.................\..\lcd1602.db_info
.................\..\lcd1602.sld_design_entry.sci
.................\..\logic_util_heursitic.dat
.................\..\lpm_divide_15m.tdf
.................\..\lpm_divide_25m.tdf
.................\..\lpm_divide_ucm.tdf
.................\..\lpm_divide_vcm.tdf
.................\..\prev_cmp_lcd1602.qmsg
.................\..\sign_div_unsign_8kh.tdf
.................\..\sign_div_unsign_9kh.tdf
.................\incremental_db
.................\..............\compiled_partitions
.................\..............\...................\lcd1602.db_info
.................\..............\...................\lcd1602.root_partition.cmp.dfp
.................\..............\...................\lcd1602.root_partition.cmp.kpt
.................\..............\...................\lcd1602.root_partition.cmp.logdb
.................\..............\...................\lcd1602.root_partition.map.dpi
.................\..............\...................\lcd1602.root_partition.map.kpt
.................\..............\README
.................\lcd1602.asm.rpt
.................\lcd1602.cdf
.................\lcd1602.done
.................\lcd1602.eda.rpt
.................\lcd1602.fit.rpt
.................\lcd1602.fit.smsg
.................\lcd1602.fit.summary
.................\lcd1602.flow.rpt
.................\lcd1602.map.rpt
.................\lcd1602.map.smsg
.................\lcd1602.map.summary
.................\lcd1602.pin
.................\lcd1602.pof
.................\lcd1602.qpf
.................\lcd1602.qsf
.................\lcd1602.sof
.................\lcd1602.sta.rpt
.................\lcd1602.sta.summary
.................\lcd1602.v
.................\lcd1602.v.bak
.................\lcd1602_assignment_defaults.qdf
.................\lcd1602_nativelink_simulation.rpt
.................\simulation
.................\..........\modelsim
.................\..........\........\gate_work
.................\..........\........\.........\_info
.................\..........\........\.........\_temp
.................\..........\........\.........\_vmake
.................\..........\........\.........\lcd1602
.................\..........\........\.........\.......\_primary.dat
.................\..........\........\.........\.......\_primary.dbs
.................\..........\........\.........\.......\_primary.vhd
.................\..........\........\.........\.......\verilog.prw
.................\..........\........\.........\.......\verilog.psm
.................\..........\........\.........\lcd1602_vlg_tst
.................\..........\........\.........\...............\_primary.dat
.................\..........\........\.........\...............\_primary.dbs
.................\..........\........\.........\...............\_primary.vhd
.................\..........\........\.........\...............\verilog.prw
.................\..........\........\.........\...............\verilog.psm
.................\..........\........\lcd1602.sft
.................\..........\........\lcd1602.vo
.................\..........\........\lcd1602.vt
.................\..........\........\lcd1602.vt.bak
.................\..........\........\lcd1602_fast.vo
.................\..........\........\lcd1602_modelsim.xrf
.................\..........\........\lcd1602_run_msim_gate_verilog.do
.................\..........\........\lcd1602_run_msim_rtl_verilog.do
.................\..........\........\lcd1602_run_msim_rtl_verilog.do.bak
.................\..........\........\lcd1602_run_msim_rtl_verilog.do.bak1
.................\..........\........\lcd1602_run_msim_rtl_verilog.do.bak2
.................\..........\........\lcd1602_run_msim_rtl_verilog.do.bak3
.................\..........\........\lcd1602_run_msim_rtl_verilog.do.bak4
.................\..........\........\lcd1602_v.sdo
.................\..........\........\lcd1602_v.sdo_typ.csd
.................\..........\........\lcd1602_v_f