文件名称:texample1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2015-10-24
  • 文件大小:
  • 894kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 日***
  • 相关连接:
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32-bit shifter, 32-bit.Very goog as a study file.-32-bit shifter, shifter, 32-bit.Very goog as a study file.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





texample1\db\logic_util_heursitic.dat

.........\..\prev_cmp_shift.qmsg

.........\..\shift.amm.cdb

.........\..\shift.asm.qmsg

.........\..\shift.asm.rdb

.........\..\shift.asm_labs.ddb

.........\..\shift.cbx.xml

.........\..\shift.cmp.cdb

.........\..\shift.cmp.hdb

.........\..\shift.cmp.kpt

.........\..\shift.cmp.logdb

.........\..\shift.cmp.rdb

.........\..\shift.cmp0.ddb

.........\..\shift.db_info

.........\..\shift.eda.qmsg

.........\..\shift.fit.qmsg

.........\..\shift.hier_info

.........\..\shift.hif

.........\..\shift.idb.cdb

.........\..\shift.lpc.html

.........\..\shift.lpc.rdb

.........\..\shift.lpc.txt

.........\..\shift.map.cdb

.........\..\shift.map.hdb

.........\..\shift.map.logdb

.........\..\shift.map.qmsg

.........\..\shift.pre_map.cdb

.........\..\shift.pre_map.hdb

.........\..\shift.rtlv.hdb

.........\..\shift.rtlv_sg.cdb

.........\..\shift.rtlv_sg_swap.cdb

.........\..\shift.sgdiff.cdb

.........\..\shift.sgdiff.hdb

.........\..\shift.sld_design_entry.sci

.........\..\shift.sld_design_entry_dsc.sci

.........\..\shift.smart_action.txt

.........\..\shift.sta.qmsg

.........\..\shift.sta.rdb

.........\..\shift.sta_cmp.5_slow.tdb

.........\..\shift.syn_hier_info

.........\..\shift.tis_db_list.ddb

.........\..\shift.tmw_info

.........\incremental_db\compiled_partitions\shift.db_info

.........\..............\...................\shift.root_partition.map.kpt

.........\..............\README

.........\shift.asm.rpt

.........\shift.done

.........\shift.eda.rpt

.........\shift.fit.rpt

.........\shift.fit.smsg

.........\shift.fit.summary

.........\shift.flow.rpt

.........\shift.map.rpt

.........\shift.map.summary

.........\shift.pin

.........\shift.pof

.........\shift.qpf

.........\shift.qsf

.........\shift.sta.rpt

.........\shift.sta.summary

.........\shift.v

.........\shift.v.bak

.........\shift_nativelink_simulation.rpt

.........\.imulation\modelsim\modelsim.ini

.........\..........\........\msim_transcript

.........\..........\........\rtl_work\shift\verilog.prw

.........\..........\........\........\.....\verilog.psm

.........\..........\........\........\.....\_primary.dat

.........\..........\........\........\.....\_primary.dbs

.........\..........\........\........\.....\_primary.vhd

.........\..........\........\........\....._vlg_tst\verilog.prw

.........\..........\........\........\.............\verilog.psm

.........\..........\........\........\.............\_primary.dat

.........\..........\........\........\.............\_primary.dbs

.........\..........\........\........\.............\_primary.vhd

.........\..........\........\........\_info

.........\..........\........\........\_vmake

.........\..........\........\shift.sft

.........\..........\........\shift.vo

.........\..........\........\shift.vt

.........\..........\........\shift.vt.bak

.........\..........\........\shift_modelsim.xrf

.........\..........\........\shift_run_msim_rtl_verilog.do

.........\..........\........\shift_run_msim_rtl_verilog.do.bak

.........\..........\........\shift_run_msim_rtl_verilog.do.bak1

.........\..........\........\shift_v.sdo

.........\..........\........\vsim.wlf

.........\..........\........\rtl_work\shift

.........\..........\........\........\shift_vlg_tst

.........\..........\........\........\_temp

.........\..........\........\rtl_work

.........\incremental_db\compiled_partitions

.........\simulation\modelsim

.........\db

.........\incremental_db

.........\simulation

texample1

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