文件名称:UART_TEST

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [HTML]
  • 上传时间:
  • 2015-10-12
  • 文件大小:
  • 3.31mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • TaeK*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

this is FPGA Verilog project
(系统自动生成,下载前可以参看下载内容)

下载文件列表





db\.cmp.kpt

..\altsyncram_9jb1.tdf

..\prev_cmp_UART_TEST.qmsg

..\UART_TEST.asm.qmsg

..\UART_TEST.asm.rdb

..\UART_TEST.asm_labs.ddb

..\UART_TEST.cbx.xml

..\UART_TEST.cmp.bpm

..\UART_TEST.cmp.cdb

..\UART_TEST.cmp.hdb

..\UART_TEST.cmp.idb

..\UART_TEST.cmp.logdb

..\UART_TEST.cmp.rdb

..\UART_TEST.cmp_merge.kpt

..\UART_TEST.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

..\UART_TEST.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd

..\UART_TEST.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd

..\UART_TEST.db_info

..\UART_TEST.eda.qmsg

..\UART_TEST.fit.qmsg

..\UART_TEST.hier_info

..\UART_TEST.hif

..\UART_TEST.logic_util_heuristic.dat

..\UART_TEST.lpc.html

..\UART_TEST.lpc.rdb

..\UART_TEST.lpc.txt

..\UART_TEST.map.ammdb

..\UART_TEST.map.bpm

..\UART_TEST.map.cdb

..\UART_TEST.map.hdb

..\UART_TEST.map.kpt

..\UART_TEST.map.logdb

..\UART_TEST.map.qmsg

..\UART_TEST.map.rdb

..\UART_TEST.map_bb.cdb

..\UART_TEST.map_bb.hdb

..\UART_TEST.map_bb.logdb

..\UART_TEST.pplq.rdb

..\UART_TEST.pre_map.hdb

..\UART_TEST.pti_db_list.ddb

..\UART_TEST.qns

..\UART_TEST.root_partition.map.reg_db.cdb

..\UART_TEST.routing.rdb

..\UART_TEST.rtlv.hdb

..\UART_TEST.rtlv_sg.cdb

..\UART_TEST.rtlv_sg_swap.cdb

..\UART_TEST.sld_design_entry.sci

..\UART_TEST.sld_design_entry_dsc.sci

..\UART_TEST.smart_action.txt

..\UART_TEST.sta.qmsg

..\UART_TEST.sta.rdb

..\UART_TEST.sta_cmp.7_slow_1200mv_85c.tdb

..\UART_TEST.tiscmp.fast_1200mv_0c.ddb

..\UART_TEST.tiscmp.slow_1200mv_0c.ddb

..\UART_TEST.tiscmp.slow_1200mv_85c.ddb

..\UART_TEST.tis_db_list.ddb

..\UART_TEST.tmw_info

..\UART_TEST.vpr.ammdb

incremental_db\compiled_partitions\UART_TEST.db_info

..............\...................\UART_TEST.root_partition.cmp.ammdb

..............\...................\UART_TEST.root_partition.cmp.cdb

..............\...................\UART_TEST.root_partition.cmp.dfp

..............\...................\UART_TEST.root_partition.cmp.hdb

..............\...................\UART_TEST.root_partition.cmp.logdb

..............\...................\UART_TEST.root_partition.cmp.rcfdb

..............\...................\UART_TEST.root_partition.map.cdb

..............\...................\UART_TEST.root_partition.map.dpi

..............\...................\UART_TEST.root_partition.map.hbdb.cdb

..............\...................\UART_TEST.root_partition.map.hbdb.hb_info

..............\...................\UART_TEST.root_partition.map.hbdb.hdb

..............\...................\UART_TEST.root_partition.map.hbdb.sig

..............\...................\UART_TEST.root_partition.map.hdb

..............\...................\UART_TEST.root_partition.map.kpt

..............\...................\UART_TEST.rrp.hdb

..............\README

output_files\Chain1.cdf

............\Chain2.cdf

............\UART_TEST.asm.rpt

............\UART_TEST.done

............\UART_TEST.eda.rpt

............\UART_TEST.fit.rpt

............\UART_TEST.fit.smsg

............\UART_TEST.fit.summary

............\UART_TEST.flow.rpt

............\UART_TEST.jdi

............\UART_TEST.map.rpt

............\UART_TEST.map.summary

............\UART_TEST.pin

............\UART_TEST.sof

............\UART_TEST.sta.rpt

............\UART_TEST.sta.summary

simulation\modelsim\UART_TEST.sft

..........\........\UART_TEST.vo

..........\........\UART_TEST_7_1200mv_0c_slow.vo

..........\........\UART_TEST_7_1200mv_0c_v_slow.sdo

..........\........\UART_TEST_7_1200mv_85c_slow.vo

..........\........\UART_TEST_7_1200mv_85c_v_slow.sdo

..........\........\UART_TEST_min_1200mv_0c_fast.vo

..........\........\UART_TEST_min_1200mv_0c_v_fast.sdo

..........\........\UART_TEST_modelsim.xrf

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