文件名称:verilog_UART
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog语言 FPGA 串口收发模块，既可以接收也可以发送，可以自行更改波特率-Verilog language FPGA serial transceiver module, I can receive can send also to change the baud rate
(系统自动生成,下载前可以参看下载内容)
下载文件列表
veriloguart
...........\db
...........\..\logic_util_heursitic.dat
...........\..\my_uart_top.amm.cdb
...........\..\my_uart_top.asm.qmsg
...........\..\my_uart_top.asm.rdb
...........\..\my_uart_top.asm_labs.ddb
...........\..\my_uart_top.cbx.xml
...........\..\my_uart_top.cmp.cdb
...........\..\my_uart_top.cmp.hdb
...........\..\my_uart_top.cmp.kpt
...........\..\my_uart_top.cmp.logdb
...........\..\my_uart_top.cmp.rdb
...........\..\my_uart_top.cmp0.ddb
...........\..\my_uart_top.db_info
...........\..\my_uart_top.eda.qmsg
...........\..\my_uart_top.fit.qmsg
...........\..\my_uart_top.hier_info
...........\..\my_uart_top.hif
...........\..\my_uart_top.idb.cdb
...........\..\my_uart_top.lpc.html
...........\..\my_uart_top.lpc.rdb
...........\..\my_uart_top.lpc.txt
...........\..\my_uart_top.map.cdb
...........\..\my_uart_top.map.hdb
...........\..\my_uart_top.map.logdb
...........\..\my_uart_top.map.qmsg
...........\..\my_uart_top.pre_map.cdb
...........\..\my_uart_top.pre_map.hdb
...........\..\my_uart_top.rpp.qmsg
...........\..\my_uart_top.rtlv.hdb
...........\..\my_uart_top.rtlv_sg.cdb
...........\..\my_uart_top.rtlv_sg_swap.cdb
...........\..\my_uart_top.sgate.rvd
...........\..\my_uart_top.sgate_sm.rvd
...........\..\my_uart_top.sgdiff.cdb
...........\..\my_uart_top.sgdiff.hdb
...........\..\my_uart_top.sld_design_entry.sci
...........\..\my_uart_top.sld_design_entry_dsc.sci
...........\..\my_uart_top.smart_action.txt
...........\..\my_uart_top.sta.qmsg
...........\..\my_uart_top.sta.rdb
...........\..\my_uart_top.sta_cmp.5_slow.tdb
...........\..\my_uart_top.syn_hier_info
...........\..\my_uart_top.tis_db_list.ddb
...........\..\my_uart_top.tmw_info
...........\..\my_uart_top_global_asgn_op.abo
...........\..\prev_cmp_my_uart_top.asm.qmsg
...........\..\prev_cmp_my_uart_top.fit.qmsg
...........\..\prev_cmp_my_uart_top.map.qmsg
...........\..\prev_cmp_my_uart_top.qmsg
...........\..\prev_cmp_my_uart_top.tan.qmsg
...........\incremental_db
...........\..............\compiled_partitions
...........\..............\...................\my_uart_top.db_info
...........\..............\...................\my_uart_top.root_partition.map.kpt
...........\..............\README
...........\my_uart_rx.v
...........\my_uart_rx.v.bak
...........\my_uart_top.asm.rpt
...........\my_uart_top.cdf
...........\my_uart_top.done
...........\my_uart_top.dpf
...........\my_uart_top.eda.rpt
...........\my_uart_top.fit.rpt
...........\my_uart_top.fit.smsg
...........\my_uart_top.fit.summary
...........\my_uart_top.flow.rpt
...........\my_uart_top.jpg
...........\my_uart_top.map.rpt
...........\my_uart_top.map.smsg
...........\my_uart_top.map.summary
...........\my_uart_top.pin
...........\my_uart_top.pof
...........\my_uart_top.qpf
...........\my_uart_top.qsf
...........\my_uart_top.qws
...........\my_uart_top.sta.rpt
...........\my_uart_top.sta.summary
...........\my_uart_top.tan.rpt
...........\my_uart_top.tan.summary
...........\my_uart_top.v
...........\my_uart_top_assignment_defaults.qdf
...........\my_uart_tx.v
...........\my_uart_tx.v.bak
...........\speed_select.v