文件名称:ecpu

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2015-09-05
  • 文件大小:
  • 613kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • Je***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

It is a type of RISC processor..it is easily reconfigurable and virtualizable.it is implemented on FPGA
(系统自动生成,下载前可以参看下载内容)

下载文件列表





ecpu\trunk\setup.sh

....\.....\components\svn-commit.tmp

....\.....\..........\adder\alu_adder.v

....\.....\..........\.lu\README

....\.....\..........\...\setup.sh

....\.....\..........\...\rtl\verilog\alu.v

....\.....\..........\...\...\.......\alu_barrel_shifter.v

....\.....\..........\...\...\.......\alu_controller.v

....\.....\..........\...\...\.......\alu_controller.vh

....\.....\..........\...\...\.......\alu_datapath.v

....\.....\..........\...\...\.......\alu_datapath.working_nosynth.v

....\.....\..........\...\...\.......\veriwell.key

....\.....\..........\...\...\.......\veriwell.log

....\.....\..........\...\...\.hdl\alu.vhd

....\.....\..........\...\...\....\alu_adder.vhd

....\.....\..........\...\...\....\alu_analog_cadence_tb.vhd

....\.....\..........\...\...\....\alu_analog_tb.vhd

....\.....\..........\...\...\....\alu_barrel_shifter.vhd

....\.....\..........\...\...\....\alu_barrel_shifter_tb.vhd

....\.....\..........\...\...\....\alu_controller.vhd

....\.....\..........\...\...\....\alu_datapath.vhd

....\.....\..........\...\...\....\alu_from_net.vhd

....\.....\..........\...\...\....\alu_stimulus.vhd

....\.....\..........\...\...\....\alu_tb.vhd

....\.....\..........\...\...\....\alu_test.txt

....\.....\..........\...\...\....\compile.simili.files

....\.....\..........\...\...\....\compile_alu.simili.files

....\.....\..........\...\...\....\do_all_simili

....\.....\..........\...\...\....\runit

....\.....\..........\...\scripts\conv_fsm.pl

....\.....\..........\...\.im\alu_tb.vcd

....\.....\..........\...\...\alu_test.txt

....\.....\..........\...\...\log

....\.....\..........\...\...\runit

....\.....\..........\...\...\run_alu

....\.....\..........\...\.ynth\check_for_synth

....\.....\..........\...\.....\veriwell.key

....\.....\..........\...\.....\veriwell.log

....\.....\..........\...\..stemc\alu_tb.v

....\.....\..........\...\.......\gen_systemc.sh

....\.....\..........\...\.......\log

....\.....\..........\...\.......\bak\Makefile

....\.....\..........\...\.......\...\verilated.cpp

....\.....\..........\...\.......\obj_dir\Makefile

....\.....\..........\...\.......\.......\run.x

....\.....\..........\...\.......\.......\sc_main.cpp

....\.....\..........\...\.......\.......\tracefile.vcd

....\.....\..........\...\.......\.......\Valu_tb.cpp

....\.....\..........\...\.......\.......\Valu_tb.h

....\.....\..........\...\.......\.......\Valu_tb.mk

....\.....\..........\...\.......\.......\Valu_tb_alu_tb.cpp

....\.....\..........\...\.......\.......\Valu_tb_alu_tb.h

....\.....\..........\...\.......\.......\Valu_tb_classes.mk

....\.....\..........\...\.......\.......\Valu_tb__ALLcls.cpp

....\.....\..........\...\.......\.......\Valu_tb__ALLcls.d

....\.....\..........\...\.......\.......\Valu_tb__ALLsup.cpp

....\.....\..........\...\.......\.......\Valu_tb__ALLsup.d

....\.....\..........\...\.......\.......\Valu_tb__Inlines.h

....\.....\..........\...\.......\.......\Valu_tb__Syms.cpp

....\.....\..........\...\.......\.......\Valu_tb__Syms.h

....\.....\..........\...\.......\.......\Valu_tb__ver.d

....\.....\..........\...\.......\.......\Valu_tb__verFiles.dat

....\.....\..........\...\.......\.......\verilated.cpp

....\.....\..........\...\.......\.......\verilog_sc.h

....\.....\..........\...\tb\alu_tb.v

....\.....\..........\barrel_shifter\simple\barrel_shifter_simple.temp.v

....\.....\..........\..............\......\barrel_shifter_simple.v

....\.....\..........\..............\......\barrel_shifter_simple.working_nosynth.v

....\.....\..........\ram\ram.v

....\.....\..........\...\ram_mk_x_n.v

....\.....\..........\.om\rom.v

....\.....\lib\dff.v

....\.....\...\mux2to1_case.v

....\.....\rtl\verilog\ecpu.v

....\.....\...\.......\ecpu_core.vh

....\.....\...\.......\ecpu_core_controller.v

....\.....\...\.......\ecpu_core_datapath.v

....\.....\...\.......\ecpu_core_generic.v

....\.....\scratch\a.out

....\.....\.......\main.c

....\.....\.im\ecpu_tb.vcd

....\.....\...\log

....\.....\...\rom_data.vh

....\.....\...\rtl.list

....\.....\...\runit.sh

....\.....\...\run_ecpu

....\.....\...\tb.list

....\.....

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