文件名称:sc2262
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Fig. 2 shows the conventional ESD protection design with
dual diodes (DPand DN) at RF I/O pad and the power-rail ESD
clamp circuit between VDDand VSS[3]. Under positive-to-VDD
(PD) or negative-to-VS
dual diodes (DPand DN) at RF I/O pad and the power-rail ESD
clamp circuit between VDDand VSS[3]. Under positive-to-VDD
(PD) or negative-to-VS
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