文件名称:spi_ipcore
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比较实用的SPI Verilog 编程，里面有仿真时序和源代码，简单改一改可直接，支持SPI双模式。-More practical SPI Verilog programming, which has simulation timing and source code, simple and can be directly altered, supports SPI dual mode.
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下载文件列表
spi_ipcore\doc\SPI_Ipcore说明文档.doc
..........\...\时序最高183M.png
..........\...\编译使用芯片以及LE使用情况.png
..........\prj\db\logic_util_heursitic.dat
..........\...\..\prev_cmp_spi_ip.qmsg
..........\...\..\spi_ip.db_info
..........\...\..\spi_ip.qns
..........\...\..\spi_ip.sas
..........\...\..\spi_ip.sld_design_entry.sci
..........\...\incremental_db\compiled_partitions\spi_ip.db_info
..........\...\..............\...................\spi_ip.root_partition.cmp.dfp
..........\...\..............\...................\spi_ip.root_partition.cmp.kpt
..........\...\..............\...................\spi_ip.root_partition.cmp.logdb
..........\...\..............\...................\spi_ip.root_partition.map.dpi
..........\...\..............\...................\spi_ip.root_partition.map.kpt
..........\...\..............\README
..........\...\spi_ip.asm.rpt
..........\...\spi_ip.done
..........\...\spi_ip.fit.rpt
..........\...\spi_ip.fit.smsg
..........\...\spi_ip.fit.summary
..........\...\spi_ip.flow.rpt
..........\...\spi_ip.map.rpt
..........\...\spi_ip.map.smsg
..........\...\spi_ip.map.summary
..........\...\spi_ip.pin
..........\...\spi_ip.qpf
..........\...\spi_ip.qsf
..........\...\spi_ip.qws
..........\...\spi_ip.sof
..........\...\spi_ip.sta.rpt
..........\...\spi_ip.sta.summary
..........\...\spi_ip_assignment_defaults.qdf
..........\sim\mode==0上升沿模式.bmp
..........\...\mode==1下降沿模式.bmp
..........\...\mode==1下降沿模式发送模式.bmp
..........\...\mode==1下降沿模式接收模式.bmp
..........\...\te.cr.mti
..........\...\te.mpf
..........\...\transcript
..........\...\vsim.wlf
..........\...\work\spi_ip\verilog.prw
..........\...\....\......\verilog.psm
..........\...\....\......\_primary.dat
..........\...\....\......\_primary.dbs
..........\...\....\......\_primary.vhd
..........\...\....\tb_spi_ip\verilog.prw
..........\...\....\.........\verilog.psm
..........\...\....\.........\_primary.dat
..........\...\....\.........\_primary.dbs
..........\...\....\.........\_primary.vhd
..........\...\....\_info
..........\...\....\.temp\vlog028zhe
..........\...\....\.....\vlog10xqw7
..........\...\....\.....\vlog845en3
..........\...\....\.....\vlog9v7xr1
..........\...\....\.....\vlogaartcx
..........\...\....\.....\vlogb0abkb
..........\...\....\.....\vlogc7hjjs
..........\...\....\.....\vlogj9efx7
..........\...\....\.....\vlogkg14rx
..........\...\....\.....\vlogt6nx4b
..........\...\....\_vmake
..........\.rc\spi_ip.v
..........\...\tb_spi_ip.v
..........\prj\incremental_db\compiled_partitions
..........\sim\work\spi_ip
..........\...\....\tb_spi_ip
..........\...\....\_temp
..........\prj\db
..........\...\incremental_db
..........\sim\work
..........\doc
..........\prj
..........\sim
..........\src
spi_ipcore