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文件名称:RISC_CPU

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [Linux] [SHELL] [源码]
  • 上传时间：
  • 2015-08-12
  • 文件大小：
  • 1.07mb
  • 下载次数：
  • 0次
  • 提 供 者：
  • 冯**
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。-This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested on the board
(系统自动生成,下载前可以参看下载内容)

下载文件列表





RISC_CPU\RISC_CPU.cache\wt\java_command_handlers.wdf

........\..............\..\synthesis.wdf

........\..............\..\webtalk_pa.xml

........\..............\..\xsim.wdf

........\.........runs\.jobs\vrs_config_1.xml

........\.............\.....\vrs_config_10.xml

........\.............\.....\vrs_config_11.xml

........\.............\.....\vrs_config_12.xml

........\.............\.....\vrs_config_13.xml

........\.............\.....\vrs_config_14.xml

........\.............\.....\vrs_config_15.xml

........\.............\.....\vrs_config_16.xml

........\.............\.....\vrs_config_17.xml

........\.............\.....\vrs_config_18.xml

........\.............\.....\vrs_config_19.xml

........\.............\.....\vrs_config_2.xml

........\.............\.....\vrs_config_20.xml

........\.............\.....\vrs_config_21.xml

........\.............\.....\vrs_config_22.xml

........\.............\.....\vrs_config_23.xml

........\.............\.....\vrs_config_24.xml

........\.............\.....\vrs_config_25.xml

........\.............\.....\vrs_config_26.xml

........\.............\.....\vrs_config_27.xml

........\.............\.....\vrs_config_28.xml

........\.............\.....\vrs_config_29.xml

........\.............\.....\vrs_config_3.xml

........\.............\.....\vrs_config_30.xml

........\.............\.....\vrs_config_31.xml

........\.............\.....\vrs_config_4.xml

........\.............\.....\vrs_config_5.xml

........\.............\.....\vrs_config_6.xml

........\.............\.....\vrs_config_7.xml

........\.............\.....\vrs_config_8.xml

........\.............\.....\vrs_config_9.xml

........\.............\impl_1\risc_cpu_5436.backup.vdi

........\.............\......\vivado_5436.backup.jou

........\.............\synth_1\.Vivado Synthesis.queue.rst

........\.............\.......\.vivado.begin.rst

........\.............\.......\.vivado.end.rst

........\.............\.......\CPU.dcp

........\.............\.......\CPU.tcl

........\.............\.......\CPU.vds

........\.............\.......\CPU_utilization_synth.pb

........\.............\.......\CPU_utilization_synth.rpt

........\.............\.......\fsm_encoding.os

........\.............\.......\gen_run.xml

........\.............\.......\hs_err_pid1192.dmp

........\.............\.......\htr.txt

........\.............\.......\ISEWrap.js

........\.............\.......\ISEWrap.sh

........\.............\.......\project.wdf

........\.............\.......\rundef.js

........\.............\.......\runme.bat

........\.............\.......\runme.log

........\.............\.......\runme.sh

........\.............\.......\test0.dat

........\.............\.......\test1.dat

........\.............\.......\test2.dat

........\.............\.......\test3.dat

........\.............\.......\testa.dat

........\.............\.......\testb.dat

........\.............\.......\testc.dat

........\.............\.......\vivado.jou

........\.............\.......\vivado.pb

........\.........sim\sim_1\behav\msim\xil_defaultlib\@c@p@u\_primary.dat

........\............\.....\.....\....\..............\......\_primary.dbs

........\............\.....\.....\....\..............\......\_primary.vhd

........\............\.....\.....\....\..............\._opt\vopt0659bk

........\............\.....\.....\....\..............\.....\vopt0jik5t

........\............\.....\.....\....\..............\.....\vopt19yc89

........\............\.....\.....\....\..............\.....\vopt1nbr2f

........\............\.....\.....\....\..............\.....\vopt1wg1e3

........\............\.....\.....\....\..............\.....\vopt2cqg5y

........\............\.....\.....\....\..............\.....\vopt2s4wz3

........\............\.....\.....\....\..............\.....\vopt2z95br

........\............\.....\.....\....\..............\.....\vopt32398d

........\............\.....\.....\....\..............\.....\vopt3fgk2j

........\............\.....\.....\....\..............\.....\vopt3wxzwr

........\............\.....\.....\....\..............\.....\vopt45wc52

........\............\.....\.....\....\..............\.....\vopt4i

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