文件名称:test_uart
- 所属分类：
- 其他小程序
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2015-07-30
- 文件大小：
- 360kb
- 下载次数：
- 0次
- 提 供 者：
- liangy*******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog 编写的串口发送和接收模块，能够设定停止位和校验位，并且包含了modelsim仿真文件。-verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test_uart\my_uart_rx.v
.........\my_uart_top.v
.........\my_uart_tx.v
.........\Readme.txt
.........\speed_select.v
.........\speed_select.v.bak
.........\tb_uart.v
.........\tb_uart.v.bak
.........\test_uart.cr.mti
.........\test_uart.mpf
.........\vsim.wlf
.........\work\my_uart_rx\verilog.prw
.........\....\..........\verilog.psm
.........\....\..........\_primary.dat
.........\....\..........\_primary.dbs
.........\....\..........\_primary.vhd
.........\....\........top\verilog.prw
.........\....\...........\verilog.psm
.........\....\...........\_primary.dat
.........\....\...........\_primary.dbs
.........\....\...........\_primary.vhd
.........\....\.........x\verilog.prw
.........\....\..........\verilog.psm
.........\....\..........\_primary.dat
.........\....\..........\_primary.dbs
.........\....\..........\_primary.vhd
.........\....\speed_select\verilog.prw
.........\....\............\verilog.psm
.........\....\............\_primary.dat
.........\....\............\_primary.dbs
.........\....\............\_primary.vhd
.........\....\tb_uart\verilog.prw
.........\....\.......\verilog.psm
.........\....\.......\_primary.dat
.........\....\.......\_primary.dbs
.........\....\.......\_primary.vhd
.........\....\_info
.........\....\.temp\vlog02kg5n
.........\....\.....\vlogdhw9w9
.........\....\.....\vlogf11vkk
.........\....\.....\vlogi1mxk6
.........\....\.....\vlogwh0wzx
.........\....\_vmake
.........\....\my_uart_rx
.........\....\my_uart_top
.........\....\my_uart_tx
.........\....\speed_select
.........\....\tb_uart
.........\....\_temp
.........\work
test_uart