文件名称:acounter
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利用VHDL语言设计的等精度数字频率计，有各个模块的详细设计语言，已调试成功。-The use of VHDL language design digital frequency meter, a detailed design language of each module has been successful debugging.
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下载文件列表
acounter
........\fenp
........\....\db
........\....\..\fenp.cbx.xml
........\....\..\fenp.cmp.cdb
........\....\..\fenp.cmp.hdb
........\....\..\fenp.cmp.logdb
........\....\..\fenp.cmp.rdb
........\....\..\fenp.db_info
........\....\..\fenp.eco.cdb
........\....\..\fenp.fit.qmsg
........\....\..\fenp.hier_info
........\....\..\fenp.hif
........\....\..\fenp.lpc.html
........\....\..\fenp.lpc.rdb
........\....\..\fenp.lpc.txt
........\....\..\fenp.map.cdb
........\....\..\fenp.map.hdb
........\....\..\fenp.map.logdb
........\....\..\fenp.map.qmsg
........\....\..\fenp.pre_map.cdb
........\....\..\fenp.pre_map.hdb
........\....\..\fenp.rtlv.hdb
........\....\..\fenp.rtlv_sg.cdb
........\....\..\fenp.rtlv_sg_swap.cdb
........\....\..\fenp.sgdiff.cdb
........\....\..\fenp.sgdiff.hdb
........\....\..\fenp.sld_design_entry.sci
........\....\..\fenp.sld_design_entry_dsc.sci
........\....\..\fenp.syn_hier_info
........\....\..\fenp.tis_db_list.ddb
........\....\..\fenp.tmw_info
........\....\fenp.done
........\....\fenp.fit.rpt
........\....\fenp.fit.summary
........\....\fenp.flow.rpt
........\....\fenp.map.eqn
........\....\fenp.map.rpt
........\....\fenp.map.summary
........\....\fenp.qpf
........\....\fenp.qsf
........\....\fenp.qws
........\....\fenp.vhd
........\....\fenp_assignment_defaults.qdf
........\....\incremental_db
........\....\..............\compiled_partitions
........\....\..............\...................\fenp.root_partition.map.kpt
........\....\..............\README
........\jishu
........\.....\db
........\.....\..\add_sub_flh.tdf
........\.....\..\jishu.cbx.xml
........\.....\..\jishu.cmp.qrpt
........\.....\..\jishu.cmp.rdb
........\.....\..\jishu.dbp
........\.....\..\jishu.db_info
........\.....\..\jishu.eco.cdb
........\.....\..\jishu.eds_overflow
........\.....\..\jishu.fnsim.cdb
........\.....\..\jishu.fnsim.hdb
........\.....\..\jishu.fnsim.qmsg
........\.....\..\jishu.hier_info
........\.....\..\jishu.hif
........\.....\..\jishu.map.cdb
........\.....\..\jishu.map.hdb
........\.....\..\jishu.map.qmsg
........\.....\..\jishu.pre_map.cdb
........\.....\..\jishu.pre_map.hdb
........\.....\..\jishu.psp
........\.....\..\jishu.rtlv.hdb
........\.....\..\jishu.rtlv_sg.cdb
........\.....\..\jishu.rtlv_sg_swap.cdb
........\.....\..\jishu.sgdiff.cdb
........\.....\..\jishu.sgdiff.hdb
........\.....\..\jishu.sim.hdb
........\.....\..\jishu.sim.qmsg
........\.....\..\jishu.sim.qrpt
........\.....\..\jishu.sim.rdb
........\.....\..\jishu.sim.vwf
........\.....\..\jishu.sld_design_entry.sci
........\.....\..\jishu.sld_design_entry_dsc.sci
........\.....\..\jishu.syn_hier_info
........\.....\jishu.done
........\.....\jishu.flow.rpt
........\.....\jishu.map.eqn
........\.....\jishu.map.rpt
........\.....\jishu.map.summary
........\.....\jishu.qpf
........\.....\jishu.qsf
........\.....\jishu.qws
........\.....\jishu.sim.rpt
........\.....\jishu.vhd
........\.....\jishu.vwf
........\menk
........\....\db
........\....\..\menk.cbx.xml
........\....\..\menk.cmp.qrpt
........\....\..\menk.cmp.rdb
........\....\..\menk.dbp
........\....\..\menk.db_info