文件名称:clock-for-nios
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基于niosⅡ的数字钟设计，适用于多种FPGA的开发板，修改管脚可移植。-NiosⅡ digital clock design is based on, for a variety of FPGA development board, modify pin portable.
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下载文件列表
基于NIOSII处理器的数字钟设计
............................\button_pio.v
............................\cmp_state.ini
............................\cpu.ocp
............................\cpu.v
............................\cpu.vo
............................\cpu_0.ocp
............................\cpu_0.v
............................\cpu_0.vo
............................\cpu_0_jtag_debug_module.v
............................\cpu_0_jtag_debug_module_wrapper.v
............................\cpu_0_ociram_default_contents.mif
............................\cpu_0_test_bench.v
............................\cpu_jtag_debug_module.v
............................\cpu_jtag_debug_module_wrapper.v
............................\cpu_ociram_default_contents.mif
............................\cpu_test_bench.v
............................\db
............................\..\sopc_led.db_info
............................\..\sopc_led.eco.cdb
............................\..\sopc_led.sld_design_entry.sci
............................\delay_reset_block.bdf
............................\jtag_uart.v
............................\jtag_uart_0.v
............................\lcd_16207_0.v
............................\led_pio.v
............................\lpm_counter0.bsf
............................\lpm_counter0.v
............................\lpm_counter0_wave0.jpg
............................\lpm_counter0_waveforms.html
............................\niosii_c.bsf
............................\niosii_c.ptf
............................\niosii_c.v
............................\niosii_c_generation_script
............................\niosii_c_log.txt
............................\niosii_c_setup_quartus.tcl
............................\niosii_c_sim
............................\............\atail-f.pl
............................\............\contents_file_warning.txt
............................\............\cpu_0_ociram_default_contents.dat
............................\............\cpu_0_ociram_default_contents.hex
............................\............\cpu_ociram_default_contents.dat
............................\............\cpu_ociram_default_contents.hex
............................\............\create_niosii_c_project.do
............................\............\ext_flash.dat
............................\............\ext_flash_lane0.dat
............................\............\ext_flash_lane1.dat
............................\............\jtag_uart_0_input_mutex.dat
............................\............\jtag_uart_0_input_stream.dat
............................\............\jtag_uart_0_log.bat
............................\............\jtag_uart_0_output_stream.dat
............................\............\jtag_uart_input_mutex.dat
............................\............\jtag_uart_input_stream.dat
............................\............\jtag_uart_log.bat
............................\............\jtag_uart_output_stream.dat
............................\............\list_presets.do
............................\............\modelsim.tcl
............................\............\onchip_ram_4K.dat
............................\............\rf_ram.dat
............................\............\rf_ram.hex
............................\............\sdram.dat
............................\............\setup_sim.do
............................\............\uart_0_input_data_mutex.dat
............................\............\uart_0_input_data_stream.dat
............................\............\uart_0_log_module.txt
............................\............\uart_input_data_mutex.dat
............................\............\uart_input_data_stream.dat
............................\............\uart_log_module.txt
............................\............\virtuals.do
............................\............\wave_presets.do
............................\onchip_ram_4K.v
............................\onchip_ram_4K_test_component.v
............................\pio_0.v
............................\pio_1.v
............................\pll.bsf
............................\pll.v
.........