文件名称:LCD1602
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Verilog 语言 CPLD 控制液晶自定义输出程序，可仿真，可转换电路原理图。-Verilog language CPLD control LCD custom output procedures, can be simulated, can be converted to circuit schematics.
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下载文件列表
LCD1602\db\.cmp.kpt
.......\..\lcd1602.asm.qmsg
.......\..\lcd1602.asm.rdb
.......\..\lcd1602.asm_labs.ddb
.......\..\lcd1602.cbx.xml
.......\..\lcd1602.cmp.cdb
.......\..\lcd1602.cmp.hdb
.......\..\lcd1602.cmp.idb
.......\..\lcd1602.cmp.logdb
.......\..\lcd1602.cmp.rdb
.......\..\lcd1602.cmp0.ddb
.......\..\lcd1602.db_info
.......\..\lcd1602.eda.qmsg
.......\..\lcd1602.fit.qmsg
.......\..\lcd1602.hier_info
.......\..\lcd1602.hif
.......\..\lcd1602.logic_util_heuristic.dat
.......\..\lcd1602.lpc.html
.......\..\lcd1602.lpc.rdb
.......\..\lcd1602.lpc.txt
.......\..\lcd1602.map.cdb
.......\..\lcd1602.map.hdb
.......\..\lcd1602.map.logdb
.......\..\lcd1602.map.qmsg
.......\..\lcd1602.map.rdb
.......\..\lcd1602.pplq.rdb
.......\..\lcd1602.pre_map.hdb
.......\..\lcd1602.pti_db_list.ddb
.......\..\lcd1602.ram0_LCD1602_4c82a4e3.hdl.mif
.......\..\lcd1602.ram1_LCD1602_4c82a4e3.hdl.mif
.......\..\lcd1602.root_partition.map.reg_db.cdb
.......\..\lcd1602.routing.rdb
.......\..\lcd1602.rtlv.hdb
.......\..\lcd1602.rtlv_sg.cdb
.......\..\lcd1602.rtlv_sg_swap.cdb
.......\..\lcd1602.sld_design_entry.sci
.......\..\lcd1602.sld_design_entry_dsc.sci
.......\..\lcd1602.smart_action.txt
.......\..\lcd1602.smp_dump.txt
.......\..\lcd1602.sta.qmsg
.......\..\lcd1602.sta.rdb
.......\..\lcd1602.sta_cmp.5_slow.tdb
.......\..\lcd1602.tis_db_list.ddb
.......\..\lcd1602.tmw_info
.......\..\lcd1602.vpr.ammdb
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_lcd1602.asm.qmsg
.......\..\prev_cmp_lcd1602.fit.qmsg
.......\..\prev_cmp_lcd1602.map.qmsg
.......\..\prev_cmp_lcd1602.qmsg
.......\..\prev_cmp_lcd1602.tan.qmsg
.......\incremental_db\compiled_partitions\lcd1602.db_info
.......\..............\...................\lcd1602.root_partition.map.kpt
.......\..............\README
.......\lcd1602.asm.rpt
.......\LCD1602.bsf
.......\lcd1602.cdf
.......\lcd1602.done
.......\lcd1602.eda.rpt
.......\lcd1602.fit.rpt
.......\lcd1602.fit.smsg
.......\lcd1602.fit.summary
.......\lcd1602.flow.rpt
.......\lcd1602.jdi
.......\lcd1602.map.rpt
.......\lcd1602.map.smsg
.......\lcd1602.map.summary
.......\lcd1602.pin
.......\lcd1602.pof
.......\lcd1602.qpf
.......\lcd1602.qsf
.......\lcd1602.qsf.bak
.......\lcd1602.qws
.......\lcd1602.sld
.......\lcd1602.sta.rpt
.......\lcd1602.sta.summary
.......\lcd1602.tan.rpt
.......\lcd1602.tan.summary
.......\LCD1602.v
.......\LCD1602.v.bak
.......\lcd1602_assignment_defaults.qdf
.......\lcd1602_nativelink_simulation.rpt
.......\LCD1602_TEST.v.bak
.......\out.bsf
.......\out.v
.......\out.v.bak
.......\simulation\modelsim\lcd1602.sft
.......\..........\........\lcd1602.vo
.......\..........\........\lcd1602_modelsim.xrf
.......\..........\........\lcd1602_run_msim_rtl_verilog.do
.......\..........\........\lcd1602_v.sdo
.......\..........\........\modelsim.ini
.......\..........\........\msim_transcript
.......\..........\........\rtl_work\_info
.......\..........\........\........\_lib.qdb
.......\..........\........\........\_lib1_0.qdb
.......\..........\........\........\_lib1_0.qpg
.......\..........\........\........\_lib1_0.qtl
.......\..........\........\........\_vmake
.......\XIANSHI.bdf