uart_all

........\clk_bps.v

........\clk_bps_read.v

........\clk_bps_read.v.bak

........\db

........\..\logic_util_heursitic.dat

........\..\prev_cmp_uart_all.qmsg

........\..\uart_all.ae.hdb

........\..\uart_all.amm.cdb

........\..\uart_all.asm.qmsg

........\..\uart_all.asm.rdb

........\..\uart_all.atom_map.rvd

........\..\uart_all.cbx.xml

........\..\uart_all.cmp.kpt

........\..\uart_all.cmp.rdb

........\..\uart_all.cmp_merge.kpt

........\..\uart_all.db_info

........\..\uart_all.eda.qmsg

........\..\uart_all.fit.qmsg

........\..\uart_all.hier_info

........\..\uart_all.hif

........\..\uart_all.idb.cdb

........\..\uart_all.lpc.html

........\..\uart_all.lpc.rdb

........\..\uart_all.lpc.txt

........\..\uart_all.map.bpm

........\..\uart_all.map.cdb

........\..\uart_all.map.hdb

........\..\uart_all.map.kpt

........\..\uart_all.map.logdb

........\..\uart_all.map.qmsg

........\..\uart_all.map.rdb

........\..\uart_all.map_bb.cdb

........\..\uart_all.map_bb.hdb

........\..\uart_all.map_bb.logdb

........\..\uart_all.pre_map.cdb

........\..\uart_all.pre_map.hdb

........\..\uart_all.root_partition.map.reg_db.cdb

........\..\uart_all.routing.rdb

........\..\uart_all.rpp.qmsg

........\..\uart_all.rtlv.hdb

........\..\uart_all.rtlv_sg.cdb

........\..\uart_all.rtlv_sg_swap.cdb

........\..\uart_all.sgate.rvd

........\..\uart_all.sgate_sm.rvd

........\..\uart_all.sgdiff.cdb

........\..\uart_all.sgdiff.hdb

........\..\uart_all.sld_design_entry.sci

........\..\uart_all.sld_design_entry_dsc.sci

........\..\uart_all.smart_action.txt

........\..\uart_all.sta.qmsg

........\..\uart_all.sta.rdb

........\..\uart_all.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd

........\..\uart_all.stingray_io_sim_cache.99um_ss_1200mv_0c_slow.hsd

........\..\uart_all.stingray_io_sim_cache.99um_ss_1200mv_85c_slow.hsd

........\..\uart_all.syn_hier_info

........\..\uart_all.tis_db_list.ddb

........\..\uart_all.tiscmp.fast_1200mv_0c.ddb

........\..\uart_all.tiscmp.fastest_slow_1200mv_0c.ddb

........\..\uart_all.tiscmp.fastest_slow_1200mv_85c.ddb

........\..\uart_all.tiscmp.slow_1200mv_0c.ddb

........\..\uart_all.tiscmp.slow_1200mv_85c.ddb

........\..\uart_all.tmw_info

........\detect.v

........\incremental_db

........\..............\README

........\..............\compiled_partitions

........\..............\...................\uart_all.db_info

........\..............\...................\uart_all.root_partition.cmp.cdb

........\..............\...................\uart_all.root_partition.cmp.dfp

........\..............\...................\uart_all.root_partition.cmp.hdb

........\..............\...................\uart_all.root_partition.cmp.kpt

........\..............\...................\uart_all.root_partition.cmp.logdb

........\..............\...................\uart_all.root_partition.cmp.rcfdb

........\..............\...................\uart_all.root_partition.map.cdb

........\..............\...................\uart_all.root_partition.map.dpi

........\..............\...................\uart_all.root_partition.map.hbdb.cdb

........\..............\...................\uart_all.root_partition.map.hbdb.hb_info

........\..............\...................\uart_all.root_partition.map.hbdb.hdb

........\..............\...................\uart_all.root_partition.map.hbdb.sig

........\..............\...................\uart_all.root_partition.map.hdb

........\..............\...................\uart_all.root_partition.map.kpt

........\read_control.v

........\simulation

........\..........\modelsim

........\..........\........\modelsim.ini

........\..........\........\msim_transcript

........\..........\........\rtl_work

........\..........\........\........\_info

........\..........\........\........\_temp

........\..........\........\........\_vmake

........\..........\........\........\clk_bps

........\..........\........\........\.......\_primary.dat

........\..........\........\........\.......\_primary.dbs

........\..........\........\........\.......\_primary.vhd

........\..........\........\........\.......\verilog.prw

........\..........\........\........\.......\v