实验7.1——基本CPU设计\实践报告.doc

......................\cpu\alu.bsf

......................\...\alu.vhd

......................\...\ar.bsf

......................\...\ar.vhd

......................\...\bus_dir.bsf

......................\...\bus_dir.vhd

......................\...\bus_mux.bsf

......................\...\bus_mux.vhd

......................\...\cmp_state.ini

......................\...\controller.bsf

......................\...\controller.vhd

......................\...\cpu0.asm.rpt

......................\...\cpu0.bdf

......................\...\cpu0.done

......................\...\cpu0.fit.eqn

......................\...\cpu0.fit.rpt

......................\...\cpu0.fit.summary

......................\...\cpu0.flow.rpt

......................\...\cpu0.map.eqn

......................\...\cpu0.map.rpt

......................\...\cpu0.map.summary

......................\...\cpu0.pin

......................\...\cpu0.pof

......................\...\cpu0.qpf

......................\...\cpu0.qsf

......................\...\cpu0.qws

......................\...\cpu0.sof

......................\...\cpu0.tan.rpt

......................\...\cpu0.tan.summary

......................\...\cpu0_assignment_defaults.qdf

......................\...\flag_reg.bsf

......................\...\flag_reg.vhd

......................\...\ir.bsf

......................\...\ir.vhd

......................\...\pc.bsf

......................\...\pc.vhd

......................\...\reg.bsf

......................\...\reg.vhd

......................\...\reg_mux.bsf

......................\...\reg_mux.vhd

......................\...\reg_out.bsf

......................\...\reg_out.vhd

......................\...\reg_test.bsf

......................\...\reg_test.vhd

......................\...\reg_testa.bsf

......................\...\reg_testa.vhd

......................\...\t1.bsf

......................\...\t1.vhd

......................\...\t2.bsf

......................\...\t2.vhd

......................\...\t3.bsf

......................\...\t3.vhd

......................\...\timer.bsf

......................\...\timer.vhd

......................\...\db\add_sub_kjh.tdf

......................\...\..\add_sub_ljh.tdf

......................\...\..\cpu0.eco.cdb

......................\...\..\cpu0.cbx.xml

......................\...\..\cpu0.sld_design_entry.sci

......................\...\..\cpu0.map.qmsg

......................\...\..\cpu0.pre_map.hdb

......................\...\..\cpu0.cmp.rdb

......................\...\..\cpu0.db_info

......................\...\..\cpu0.pre_map.cdb

......................\...\..\cpu0.hier_info

......................\...\..\cpu0.hif

......................\...\..\cpu0.rtlv.hdb

......................\...\..\cpu0.rtlv_sg.cdb

......................\...\..\cpu0.rtlv_sg_swap.cdb

......................\...\..\cpu0.sld_design_entry_dsc.sci

......................\...\..\cpu0.psp

......................\...\..\cpu0.fit.qmsg

......................\...\..\cpu0.sgdiff.cdb

......................\...\..\cpu0.map.hdb

......................\...\..\cpu0.sgdiff.hdb

......................\...\..\cpu0.map.cdb

......................\...\..\cpu0.cmp0.ddb

......................\...\..\cpu0.cmp.cdb

......................\...\..\cpu0.cmp.hdb

......................\...\..\cpu0.asm.qmsg

......................\...\..\cpu0.smp_dump.txt

......................\...\..\cpu0.syn_hier_info

......................\...\..\cpu0.tan.qmsg

......................\...\..\cpu0_cmp.qrpt

......................\...\..\cpu0.signalprobe.cdb

......................\...\..\cpu0.cmp.tdb

......................\...\cpu0.cdf

......................\.onfig&samples\cpu.txt

......................\..............\ex1.txt

......................\..............\ex2.txt

......................\..............\ex3.txt

......................\..............\123.txt

......................\.pu\db

......................\cpu

......................\config&samples

实验7.1——基本CPU设计