文件名称:start_lab4
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用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数-
Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
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下载文件列表
start_lab4
..........\db
..........\..\altsyncram_iss3.tdf
..........\..\altsyncram_ups3.tdf
..........\..\cmpr_efc.tdf
..........\..\cmpr_gfc.tdf
..........\..\cmpr_hfc.tdf
..........\..\cntr_0fi.tdf
..........\..\cntr_22j.tdf
..........\..\cntr_5fi.tdf
..........\..\cntr_95j.tdf
..........\..\cntr_ldi.tdf
..........\..\cntr_odi.tdf
..........\..\cntr_p1j.tdf
..........\..\dec_segment.asm.qmsg
..........\..\dec_segment.asm.rdb
..........\..\dec_segment.asm_labs.ddb
..........\..\dec_segment.cbx.xml
..........\..\dec_segment.cmp.bpm
..........\..\dec_segment.cmp.cdb
..........\..\dec_segment.cmp.ecobp
..........\..\dec_segment.cmp.hdb
..........\..\dec_segment.cmp.kpt
..........\..\dec_segment.cmp.logdb
..........\..\dec_segment.cmp.rdb
..........\..\dec_segment.cmp_merge.kpt
..........\..\dec_segment.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
..........\..\dec_segment.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
..........\..\dec_segment.db_info
..........\..\dec_segment.eco.cdb
..........\..\dec_segment.fit.qmsg
..........\..\dec_segment.hier_info
..........\..\dec_segment.hif
..........\..\dec_segment.lpc.html
..........\..\dec_segment.lpc.rdb
..........\..\dec_segment.lpc.txt
..........\..\dec_segment.map.bpm
..........\..\dec_segment.map.cdb
..........\..\dec_segment.map.ecobp
..........\..\dec_segment.map.hdb
..........\..\dec_segment.map.kpt
..........\..\dec_segment.map.logdb
..........\..\dec_segment.map.qmsg
..........\..\dec_segment.map_bb.cdb
..........\..\dec_segment.map_bb.hdb
..........\..\dec_segment.map_bb.logdb
..........\..\dec_segment.pre_map.cdb
..........\..\dec_segment.pre_map.hdb
..........\..\dec_segment.rtlv.hdb
..........\..\dec_segment.rtlv_sg.cdb
..........\..\dec_segment.rtlv_sg_swap.cdb
..........\..\dec_segment.sgdiff.cdb
..........\..\dec_segment.sgdiff.hdb
..........\..\dec_segment.sld_design_entry.sci
..........\..\dec_segment.sld_design_entry_dsc.sci
..........\..\dec_segment.smart_action.txt
..........\..\dec_segment.sta.qmsg
..........\..\dec_segment.sta.rdb
..........\..\dec_segment.sta_cmp.6_slow_1200mv_85c.tdb
..........\..\dec_segment.syn_hier_info
..........\..\dec_segment.tis_db_list.ddb
..........\..\dec_segment.tiscmp.fast_1200mv_0c.ddb
..........\..\dec_segment.tiscmp.slow_1200mv_0c.ddb
..........\..\dec_segment.tiscmp.slow_1200mv_85c.ddb
..........\..\dec_segment.tmw_info
..........\..\dec_segment1.asm.qmsg
..........\..\dec_segment1.asm.rdb
..........\..\dec_segment1.asm_labs.ddb
..........\..\dec_segment1.cbx.xml
..........\..\dec_segment1.cmp.bpm
..........\..\dec_segment1.cmp.cdb
..........\..\dec_segment1.cmp.ecobp
..........\..\dec_segment1.cmp.hdb
..........\..\dec_segment1.cmp.kpt
..........\..\dec_segment1.cmp.logdb
..........\..\dec_segment1.cmp.rdb
..........\..\dec_segment1.cmp_merge.kpt
..........\..\dec_segment1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
..........\..\dec_segment1.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
..........\..\dec_segment1.db_info
..........\..\dec_segment1.eco.cdb
..........\..\dec_segment1.fit.qmsg
..........\..\dec_segment1.hier_info
..........\..\dec_segment1.hif
..........\..\dec_segment1.lpc.html
..........\..\dec_segment1.lpc.rdb
..........\..\dec_segment1.lpc.txt
..........\..\dec_segment1.map.bpm
..........\..\dec_segment1.map.cdb
..........\..\dec_segment1.map.ecobp
..........\..\dec_segment1.map.hdb
..........\..\dec_segment1.map.kpt
..........\..\dec_segment1.map.logdb
..........\..\dec_segment1.map.qmsg
..........\..\dec_segment1.map_bb.cdb
..........\..\dec_segment1.map_bb.hdb
..........\..\dec_segment1.map_bb.logdb
..........\..\dec_segment1.pre_map.cdb
..........\..\dec_segment1.pre_map.hdb
..........\..\dec_segment1.rtlv.hdb