文件名称:lab1_multicycle_dds
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生成一个多周期直接信号数字合成器的Verilog代码，已在matlab中测试生成信号的频谱纯度符号要求-Generate more than one cycle of the signal direct digital synthesizer Verilog code, has been tested symbol require spectral purity of the signal generated in matlab
(系统自动生成,下载前可以参看下载内容)
下载文件列表
lab1_multicycle_dds
...................\design_file
...................\...........\lab_top.bdf
...................\...........\mc_dds.v
...................\...........\mc_dds.v.bak
...................\...........\rtl_module.v
...................\...........\sine_rom.v
...................\pin_de0.txt
...................\project_q72
...................\...........\cfftwinplot.m
...................\...........\cnt_0to9.bsf
...................\...........\cnt_en_0to9.bsf
...................\...........\cnt_incr.bsf
...................\...........\cnt_sync.bsf
...................\...........\db
...................\...........\..\altsyncram_2571.tdf
...................\...........\..\altsyncram_gvs3.tdf
...................\...........\..\cmpr_ffc.tdf
...................\...........\..\cmpr_ifc.tdf
...................\...........\..\cntr_6fi.tdf
...................\...........\..\cntr_gdi.tdf
...................\...........\..\cntr_v7j.tdf
...................\...........\..\lab_top.asm.qmsg
...................\...........\..\lab_top.asm.rdb
...................\...........\..\lab_top.asm_labs.ddb
...................\...........\..\lab_top.cbx.xml
...................\...........\..\lab_top.cmp.bpm
...................\...........\..\lab_top.cmp.cbp
...................\...........\..\lab_top.cmp.cdb
...................\...........\..\lab_top.cmp.ecobp
...................\...........\..\lab_top.cmp.hdb
...................\...........\..\lab_top.cmp.kpt
...................\...........\..\lab_top.cmp.logdb
...................\...........\..\lab_top.cmp.rdb
...................\...........\..\lab_top.cmp_merge.kpt
...................\...........\..\lab_top.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
...................\...........\..\lab_top.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
...................\...........\..\lab_top.db_info
...................\...........\..\lab_top.eco.cdb
...................\...........\..\lab_top.fit.qmsg
...................\...........\..\lab_top.hier_info
...................\...........\..\lab_top.hif
...................\...........\..\lab_top.lpc.html
...................\...........\..\lab_top.lpc.rdb
...................\...........\..\lab_top.lpc.txt
...................\...........\..\lab_top.map.bpm
...................\...........\..\lab_top.map.cdb
...................\...........\..\lab_top.map.ecobp
...................\...........\..\lab_top.map.hdb
...................\...........\..\lab_top.map.kpt
...................\...........\..\lab_top.map.logdb
...................\...........\..\lab_top.map.qmsg
...................\...........\..\lab_top.map_bb.cdb
...................\...........\..\lab_top.map_bb.hdb
...................\...........\..\lab_top.map_bb.logdb
...................\...........\..\lab_top.pre_map.cdb
...................\...........\..\lab_top.pre_map.hdb
...................\...........\..\lab_top.rom0_sine_rom_d6b5acbf.hdl.mif
...................\...........\..\lab_top.rpp.qmsg
...................\...........\..\lab_top.rtlv.hdb
...................\...........\..\lab_top.rtlv_sg.cdb
...................\...........\..\lab_top.rtlv_sg_swap.cdb
...................\...........\..\lab_top.sgate.rvd
...................\...........\..\lab_top.sgate_sm.rvd
...................\...........\..\lab_top.sgdiff.cdb
...................\...........\..\lab_top.sgdiff.hdb
...................\...........\..\lab_top.sld_design_entry.sci
...................\...........\..\lab_top.sld_design_entry_dsc.sci
...................\...........\..\lab_top.smart_action.txt
...................\...........\..\lab_top.sta.qmsg
...................\...........\..\lab_top.sta.rdb
...................\...........\..\lab_top.sta_cmp.6_slow_1200mv_85c.tdb
...................\...........\..\lab_top.syn_hier_info
...................\...........\..\lab_top.tis_db_list.ddb
...................\...........\..\lab_top.tiscmp.fast_1200mv_0c.ddb
...................\...........\..\lab_top.tiscmp.slow_1200mv_0c.ddb
...................\...........\..\lab_top.tiscmp.slow_1200mv_85c.ddb
...................\...........\..\logic_u