文件名称:EDA
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采用一种基于FPGA的IIR数字滤波器的设计方案,通过QuartusⅡ的设计平台，采用自顶向下的模块化设计思想将整个IIR数字滤波器分为：时序控制、延时、补码乘加和累加四个功能模块。分别对各模块采用VHDL进行描述后，进行了仿真和综合。-IIR digital filter using a FPGA-based design, analyzes the theory and design method of IIR digital filter, then through QuartusⅡ design platform, using a top-down modular design the entire IIR digital filter divided into: timing control, delay, complement multiply and accumulate four functional modules. Respectively, after each module using VHDL descr iption, simulation and synthesis.
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下载文件列表
EDA
...\IRR1
...\....\IRR1.bdf
...\....\IRR1.flow.rpt
...\....\IRR1.map.rpt
...\....\IRR1.map.summary
...\....\IRR1.qpf
...\....\IRR1.qsf
...\....\IRR1.qws
...\....\addyn.vhd
...\....\addyn.vhd.bak
...\....\control.vhd
...\....\control.vhd.bak
...\....\db
...\....\..\IRR1.cbx.xml
...\....\..\IRR1.cmp.rdb
...\....\..\IRR1.db_info
...\....\..\IRR1.eco.cdb
...\....\..\IRR1.hif
...\....\..\IRR1.map.qmsg
...\....\..\IRR1.map_bb.hdb
...\....\..\IRR1.sld_design_entry.sci
...\....\..\IRR1.tis_db_list.ddb
...\....\..\prev_cmp_IRR1.map.qmsg
...\....\..\prev_cmp_IRR1.qmsg
...\....\delay.vhd
...\....\delay.vhd.bak
...\....\incremental_db
...\....\..............\README
...\....\..............\compiled_partitions
...\....\smultadd1.vhd
...\....\smultadd1.vhd.bak
...\addyn
...\.....\addyn.asm.rpt
...\.....\addyn.bdf
...\.....\addyn.bsf
...\.....\addyn.done
...\.....\addyn.fit.rpt
...\.....\addyn.fit.smsg
...\.....\addyn.fit.summary
...\.....\addyn.flow.rpt
...\.....\addyn.map.rpt
...\.....\addyn.map.summary
...\.....\addyn.pin
...\.....\addyn.pof
...\.....\addyn.qpf
...\.....\addyn.qsf
...\.....\addyn.qws
...\.....\addyn.sim.rpt
...\.....\addyn.sof
...\.....\addyn.tan.rpt
...\.....\addyn.tan.summary
...\.....\addyn.vhd
...\.....\addyn.vhd.bak
...\.....\addyn.vwf
...\.....\db
...\.....\..\addyn.asm.qmsg
...\.....\..\addyn.asm_labs.ddb
...\.....\..\addyn.cbx.xml
...\.....\..\addyn.cmp.bpm
...\.....\..\addyn.cmp.cdb
...\.....\..\addyn.cmp.ecobp
...\.....\..\addyn.cmp.hdb
...\.....\..\addyn.cmp.kpt
...\.....\..\addyn.cmp.logdb
...\.....\..\addyn.cmp.rdb
...\.....\..\addyn.cmp.tdb
...\.....\..\addyn.cmp0.ddb
...\.....\..\addyn.cmp2.ddb
...\.....\..\addyn.cmp_merge.kpt
...\.....\..\addyn.db_info
...\.....\..\addyn.eco.cdb
...\.....\..\addyn.eds_overflow
...\.....\..\addyn.fit.qmsg
...\.....\..\addyn.hier_info
...\.....\..\addyn.hif
...\.....\..\addyn.lpc.html
...\.....\..\addyn.lpc.rdb
...\.....\..\addyn.lpc.txt
...\.....\..\addyn.map.bpm
...\.....\..\addyn.map.cdb
...\.....\..\addyn.map.ecobp
...\.....\..\addyn.map.hdb
...\.....\..\addyn.map.kpt
...\.....\..\addyn.map.logdb
...\.....\..\addyn.map.qmsg
...\.....\..\addyn.map_bb.cdb
...\.....\..\addyn.map_bb.hdb
...\.....\..\addyn.map_bb.logdb
...\.....\..\addyn.pre_map.cdb
...\.....\..\addyn.pre_map.hdb
...\.....\..\addyn.rtlv.hdb
...\.....\..\addyn.rtlv_sg.cdb
...\.....\..\addyn.rtlv_sg_swap.cdb
...\.....\..\addyn.sgdiff.cdb
...\.....\..\addyn.sgdiff.hdb
...\.....\..\addyn.sim.cvwf
...\.....\..\addyn.sim.hdb
...\.....\..\addyn.sim.qmsg
...\.....\..\addyn.sim.rdb