文件名称:Elham-Zahraei-Salehi_-Sina-Saharkhiz-(1)
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here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
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Elham Zahraei Salehi_ Sina Saharkhiz
....................................\ALU.v
....................................\Branch_Data_Forwarding.v
....................................\Branch_Data_Forwarding.v.bak
....................................\Branch_pred.v
....................................\Controller.v
....................................\Controller.v.bak
....................................\data_mem.txt
....................................\EX_MEM.v
....................................\EX_MEM.v.bak
....................................\EX_MEM_DataForwarding.v
....................................\ID_EX.v
....................................\ID_EX.v.bak
....................................\IF_ID.v
....................................\InstMem.v
....................................\inst_mem.txt
....................................\MemData.v
....................................\MEM_WB.v
....................................\pc.v
....................................\pipeline.cr.mti
....................................\pipeline.mpf
....................................\Processor.v
....................................\Processor.v.bak
....................................\ProcessorTest.v
....................................\RegFile.v
....................................\RegFile.v.bak
....................................\tcl_stacktrace.txt
....................................\testDescription.txt
....................................\vsim.wlf
....................................\work
....................................\....\@a@l@u
....................................\....\......\verilog.prw
....................................\....\......\verilog.psm
....................................\....\......\_primary.dat
....................................\....\......\_primary.dbs
....................................\....\......\_primary.vhd
....................................\....\@branch@data@forwarding
....................................\....\.......................\verilog.prw
....................................\....\.......................\verilog.psm
....................................\....\.......................\_primary.dat
....................................\....\.......................\_primary.dbs
....................................\....\.......................\_primary.vhd
....................................\....\@branchpred
....................................\....\...........\verilog.prw
....................................\....\...........\verilog.psm
....................................\....\...........\_primary.dat
....................................\....\...........\_primary.dbs
....................................\....\...........\_primary.vhd
....................................\....\@controller
....................................\....\...........\verilog.prw
....................................\....\...........\verilog.psm
....................................\....\...........\_primary.dat
....................................\....\...........\_primary.dbs
....................................\....\...........\_primary.vhd
....................................\....\@data@memory
....................................\....\............\verilog.prw
....................................\....\............\verilog.psm
....................................\....\............\_primary.dat
....................................\....\............\_primary.dbs
....................................\....\............\_primary.vhd
....................................\....\@e@x_@m@e@m
....................................\....\...........\verilog.prw
....................................\....\...........\verilog.psm
....................................\....\...........\_primary.dat
....................................\....\...........\_primary.dbs
....................................\....\...........\_primary.vhd
....................................\....\@ex_@mem@data@forwarding
....................................\....\........................\verilog.prw
....................................\....\........................\verilog.psm