文件名称:div
介绍说明－－下载内容均来自于网络，请自行研究使用
使用quartusII软件，Verilog语言编写的一个分频器，仿真测试通过- frequency dividing circuit
(系统自动生成,下载前可以参看下载内容)
下载文件列表
div\db\div.asm.qmsg
...\..\div.asm.rdb
...\..\div.cbx.xml
...\..\div.cmp.idb
...\..\div.cmp.kpt
...\..\div.cmp.rdb
...\..\div.cmp0.ddb
...\..\div.cmp_merge.kpt
...\..\div.db_info
...\..\div.fit.qmsg
...\..\div.hier_info
...\..\div.hif
...\..\div.ipinfo
...\..\div.lpc.html
...\..\div.lpc.rdb
...\..\div.lpc.txt
...\..\div.map.ammdb
...\..\div.map.bpm
...\..\div.map.cdb
...\..\div.map.hdb
...\..\div.map.kpt
...\..\div.map.logdb
...\..\div.map.qmsg
...\..\div.map.rdb
...\..\div.map_bb.cdb
...\..\div.map_bb.hdb
...\..\div.map_bb.logdb
...\..\div.pre_map.hdb
...\..\div.pti_db_list.ddb
...\..\div.root_partition.map.reg_db.cdb
...\..\div.routing.rdb
...\..\div.rpp.qmsg
...\..\div.rtlv.hdb
...\..\div.rtlv_sg.cdb
...\..\div.rtlv_sg_swap.cdb
...\..\div.sgate.rvd
...\..\div.sgate_sm.rvd
...\..\div.sgdiff.cdb
...\..\div.sgdiff.hdb
...\..\div.sld_design_entry.sci
...\..\div.sld_design_entry_dsc.sci
...\..\div.smart_action.txt
...\..\div.sta.qmsg
...\..\div.sta.rdb
...\..\div.syn_hier_info
...\..\div.tis_db_list.ddb
...\..\div.tmw_info
...\..\div.vpr.ammdb
...\..\logic_util_heursitic.dat
...\..\prev_cmp_div.qmsg
...\div.qpf
...\div.qsf
...\div.qws
...\div.v
...\div.v.bak
...\incremental_db\compiled_partitions\div.db_info
...\..............\...................\div.root_partition.cmp.ammdb
...\..............\...................\div.root_partition.cmp.cdb
...\..............\...................\div.root_partition.cmp.dfp
...\..............\...................\div.root_partition.cmp.hdb
...\..............\...................\div.root_partition.cmp.kpt
...\..............\...................\div.root_partition.cmp.logdb
...\..............\...................\div.root_partition.cmp.rcfdb
...\..............\...................\div.root_partition.map.cdb
...\..............\...................\div.root_partition.map.dpi
...\..............\...................\div.root_partition.map.hbdb.cdb
...\..............\...................\div.root_partition.map.hbdb.hb_info
...\..............\...................\div.root_partition.map.hbdb.hdb
...\..............\...................\div.root_partition.map.hbdb.sig
...\..............\...................\div.root_partition.map.hdb
...\..............\...................\div.root_partition.map.kpt
...\..............\README
...\output_files\div.asm.rpt
...\............\div.done
...\............\div.fit.rpt
...\............\div.fit.smsg
...\............\div.fit.summary
...\............\div.flow.rpt
...\............\div.jdi
...\............\div.map.rpt
...\............\div.map.summary
...\............\div.pin
...\............\div.pof
...\............\div.sof
...\............\div.sta.rpt
...\............\div.sta.summary
...\simulation\div_tb.cr.mti
...\..........\div_tb.mpf
...\..........\div_tb.v
...\..........\div_tb.v.bak
...\..........\vsim.wlf
...\..........\work\div\verilog.prw
...\..........\....\...\verilog.psm
...\..........\....\...\_primary.dat
...\..........\....\...\_primary.dbs
...\..........\....\...\_primary.vhd
...\..........\....\..._tb\verilog.prw
...\..........\....\......\verilog.psm
...\..........\....\......\_primary.dat
...\..........\....\......\_primary.dbs