文件名称:Random-number-generator-verilog
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Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
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下载文件列表
110445D_DSD_Individual
......................\110445D_individual report.pdf
......................\13bit_lfsr.circ
......................\13bit_lfsr.jpg
......................\4bit_lfsr.JPG
......................\Code
......................\....\lfsr.v
......................\....\sseg.v
......................\netlist.JPG
......................\RTL_3.png
......................\schematic.pdf
......................\Simulation.JPG
......................\Simulation.wcfg
......................\summary.JPG
......................\tech1.png
......................\testbench
......................\.........\lfsr_rng_test.v
......................\ucf
......................\...\lfsr_rng.ucf