文件名称:lab6
介绍说明－－下载内容均来自于网络，请自行研究使用
详细描述设计过程和实验中遇到的问题，包括：
① 指令格式设计
② 微操作的定义
③ 节拍的划分
④ 处理器详细结构设计框图及功能描述(评分重点)
a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及.
b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上
⑤ 各功能模块结构设计框图及功能描述（评分重点）
⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义）
实验总结，在调试和下载过程中遇到的问题
-A detailed descr iption of the design process and problems encountered in the experiment, including:. ① ② micro-operation instruction format design definition ③ ④ processor division beat detailed descr iption of the structural design and function block diagram (score focus) a single-wire connection between modules with a thin, two more than the number indicated by bold lines and and. b. Use the arrow indicating the flow of data, signal names used when instantiated ⑤ shall be marked on the connection of each functional module design and function block diagram and descr iption (Ratings Key) ⑥ VHDL code, UCF file, test instruction sequence (the meaning of each instruction) experiments summarized problems encountered during commissioning and download the
① 指令格式设计
② 微操作的定义
③ 节拍的划分
④ 处理器详细结构设计框图及功能描述(评分重点)
a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及.
b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上
⑤ 各功能模块结构设计框图及功能描述（评分重点）
⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义）
实验总结，在调试和下载过程中遇到的问题
-A detailed descr iption of the design process and problems encountered in the experiment, including:. ① ② micro-operation instruction format design definition ③ ④ processor division beat detailed descr iption of the structural design and function block diagram (score focus) a single-wire connection between modules with a thin, two more than the number indicated by bold lines and and. b. Use the arrow indicating the flow of data, signal names used when instantiated ⑤ shall be marked on the connection of each functional module design and function block diagram and descr iption (Ratings Key) ⑥ VHDL code, UCF file, test instruction sequence (the meaning of each instruction) experiments summarized problems encountered during commissioning and download the
(系统自动生成,下载前可以参看下载内容)
下载文件列表
lab6
....\newdata2.dat
....\newnewcpu
....\.........\alu.vhd
....\.........\bstest.ant
....\.........\bstest.fdo
....\.........\bstest.jhd
....\.........\bstest.tbw
....\.........\bstest.udo
....\.........\bstest.vhw
....\.........\bstest.xwv
....\.........\bstest.xwv_bak
....\.........\bstest_bencher.prj
....\.........\count5.vhd
....\.........\cpu.bgn
....\.........\cpu.bit
....\.........\cpu.bld
....\.........\cpu.cel
....\.........\cpu.cmd_log
....\.........\cpu.drc
....\.........\cpu.fdo
....\.........\cpu.lfp
....\.........\cpu.lso
....\.........\cpu.ncd
....\.........\cpu.ngc
....\.........\cpu.ngd
....\.........\cpu.ngr
....\.........\cpu.pad
....\.........\cpu.par
....\.........\cpu.pcf
....\.........\cpu.prj
....\.........\cpu.stx
....\.........\cpu.syr
....\.........\cpu.twr
....\.........\cpu.twx
....\.........\cpu.ucf
....\.........\cpu.udo
....\.........\cpu.unroutes
....\.........\cpu.ut
....\.........\cpu.vhd
....\.........\cpu.xpi
....\.........\cpu.xst
....\.........\cpu_guide.ncd
....\.........\cpu_map.map
....\.........\cpu_map.mrp
....\.........\cpu_map.ncd
....\.........\cpu_map.ngm
....\.........\cpu_pad.csv
....\.........\cpu_pad.txt
....\.........\cpu_prev_built.ngd
....\.........\cpu_summary.html
....\.........\cpu_summary.xml
....\.........\cpu_usage.xml
....\.........\cpu_vhdl.prj
....\.........\device_usage_statistics.html
....\.........\irctl.vhd
....\.........\memctl.vhd
....\.........\memory.vhd
....\.........\newnewcpu.ise
....\.........\newnewcpu.ise_ISE_Backup
....\.........\newnewcpu.ntrc_log
....\.........\pepExtractor.prj
....\.........\results.txt
....\.........\rewrite.vhd
....\.........\test2.jhd
....\.........\test2.tbw
....\.........\test2_bencher.prj
....\.........\testalu.ant
....\.........\testalu.fdo
....\.........\testalu.jhd
....\.........\testalu.tbw
....\.........\testalu.udo
....\.........\testalu.vhw
....\.........\testalu.xwv
....\.........\testalu.xwv_bak
....\.........\testalu_bencher.prj
....\.........\testclk.ant
....\.........\testclk.fdo
....\.........\testclk.jhd
....\.........\testclk.tbw
....\.........\testclk.udo
....\.........\testclk.xwv
....\.........\testclk.xwv_bak
....\.........\testclk_bencher.prj
....\.........\testir.ant
....\.........\testir.fdo
....\.........\testir.jhd
....\.........\testir.tbw
....\.........\testir.udo
....\.........\testir.xwv
....\.........\testir.xwv_bak
....\.........\testir_bencher.prj
....\.........\testmemctl.ant
....\.........\testmemctl.fdo
....\.........\testmemctl.jhd
....\.........\testmemctl.tbw
....\.........\testmemctl.udo
....\.........\testmemctl.xwv
....\.........\testmemctl.xwv_bak
....\.........\testmemctl_bencher.prj