文件名称:Project-8
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课程设计时用verilogHDL写的MIPS CPU-MIPS CPU coded with Verilog HDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Project 8
.........\ALU.v
.........\ALU.v.bak
.........\ALU_simple.v
.........\BE.v
.........\BE.v.bak
.........\BIT_N.v
.........\BIT_N.v.bak
.........\bridge.v
.........\bridge.v.bak
.........\buffer.v
.........\buffer.v.bak
.........\code.txt
.........\code1.txt
.........\code3.txt
.........\code3_1.txt
.........\code3_2.txt
.........\code3_3.txt
.........\code4.txt
.........\compare.v
.........\compare.v.bak
.........\control.v
.........\control.v.bak
.........\control_1.v.bak
.........\CP0.v
.........\CP0.v.bak
.........\data.txt
.........\data1.txt
.........\data3.txt
.........\data3_2.txt
.........\data3_3.txt
.........\data4.txt
.........\datapath.v
.........\datapath.v.bak
.........\datapath_1.v.bak
.........\dm.v
.........\dm.v.bak
.........\dm_1.v.bak
.........\EXT.v
.........\EXT.v.bak
.........\EXT_1.v.bak
.........\GPR.v
.........\GPR.v.bak
.........\head_mips.v
.........\head_mips.v.bak
.........\im.v
.........\im.v.bak
.........\MDtest.txt
.........\mini_machine.v
.........\mini_machine.v.bak
.........\mips.v
.........\mips.v.bak
.........\mips_1.v.bak
.........\MulAndDiv.v
.........\MulAndDiv.v.bak
.........\MUX.v
.........\MUX.v.bak
.........\NPC.v
.........\NPC.v.bak
.........\NPC_1.v.bak
.........\PC.v
.........\PC.v.bak
.........\PC_1.v.bak
.........\SHIFT.v
.........\SHIFT.v.bak
.........\tcl_stacktrace.txt
.........\test.txt
.........\testbench_mips.v
.........\testbench_mips.v.bak
.........\Timer_Counter.v
.........\Timer_Counter.v.bak
.........\transcript
.........\vsim.wlf
.........\wlft02srfm
.........\wlft04rwch
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.........\wlft1jf71y
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