文件名称:edasingene
介绍说明－－下载内容均来自于网络，请自行研究使用
基于FPGA的正弦信号发生器的设计，用verilog语言实现，可调整频率和周期。-FPGA design based on sinusoidal signal generator with verilog language, adjust the frequency and period.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
edasingene\cmp_state.ini
..........\datarom.bsf
..........\datarom.v
..........\datarom_bb.v
..........\.b\add_sub_2qg.tdf
..........\..\add_sub_3qg.tdf
..........\..\add_sub_498.tdf
..........\..\add_sub_598.tdf
..........\..\add_sub_5ih.tdf
..........\..\add_sub_658.tdf
..........\..\add_sub_698.tdf
..........\..\add_sub_798.tdf
..........\..\add_sub_87h.tdf
..........\..\add_sub_898.tdf
..........\..\add_sub_a7h.tdf
..........\..\add_sub_brg.tdf
..........\..\add_sub_ilh.tdf
..........\..\add_sub_j7c.tdf
..........\..\add_sub_k7c.tdf
..........\..\add_sub_l7c.tdf
..........\..\add_sub_l8h.tdf
..........\..\add_sub_m7c.tdf
..........\..\add_sub_n7c.tdf
..........\..\add_sub_o8h.tdf
..........\..\add_sub_pah.tdf
..........\..\add_sub_plh.tdf
..........\..\alt_u_div_gie.tdf
..........\..\alt_u_div_rfd.tdf
..........\..\lpm_divide_qvl.tdf
..........\..\lpm_divide_vff.tdf
..........\..\mult_0f01.tdf
..........\..\mult_2f01.tdf
..........\..\mux_s9c.tdf
..........\..\prev_cmp_singene.map.qmsg
..........\..\prev_cmp_singene.qmsg
..........\..\sign_div_unsign_6kh.tdf
..........\..\sign_div_unsign_hhg.tdf
..........\..\singene.asm.qmsg
..........\..\singene.cbx.xml
..........\..\singene.cmp.cdb
..........\..\singene.cmp.hdb
..........\..\singene.cmp.logdb
..........\..\singene.cmp.rdb
..........\..\singene.cmp.tdb
..........\..\singene.cmp0.ddb
..........\..\singene.db_info
..........\..\singene.eco.cdb
..........\..\singene.eds_overflow
..........\..\singene.fit.qmsg
..........\..\singene.fnsim.cdb
..........\..\singene.fnsim.hdb
..........\..\singene.fnsim.qmsg
..........\..\singene.hier_info
..........\..\singene.hif
..........\..\singene.lpc.html
..........\..\singene.lpc.rdb
..........\..\singene.lpc.txt
..........\..\singene.map.cdb
..........\..\singene.map.hdb
..........\..\singene.map.logdb
..........\..\singene.map.qmsg
..........\..\singene.pre_map.cdb
..........\..\singene.pre_map.hdb
..........\..\singene.rtlv.hdb
..........\..\singene.rtlv_sg.cdb
..........\..\singene.rtlv_sg_swap.cdb
..........\..\singene.sgdiff.cdb
..........\..\singene.sgdiff.hdb
..........\..\singene.sim.cvwf
..........\..\singene.sim.hdb
..........\..\singene.sim.qmsg
..........\..\singene.sim.rdb
..........\..\singene.sim.vwf
..........\..\singene.simfam
..........\..\singene.sld_design_entry.sci
..........\..\singene.sld_design_entry_dsc.sci
..........\..\singene.syn_hier_info
..........\..\singene.tan.qmsg
..........\..\singene.tis_db_list.ddb
..........\..\singene.tmw_info
..........\..\singene_cmp.qrpt
..........\..\singene_sim.qrpt
..........\..\wed.wsf
..........\incremental_db\compiled_partitions\singene.root_partition.map.kpt
..........\..............\README
..........\romd.mif
..........\singene.asm.rpt
..........\singene.done
..........\singene.fit.eqn
..........\singene.fit.rpt
..........\singene.fit.summary
..........\singene.flow.rpt
..........\singene.map.eqn
..........\singene.map.rpt
..........\singene.map.summary
..........\singene.pin
..........\singene.pof
..........\singene.qpf
..........\singene.qsf
..........\singene.qws