文件名称:count4
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计数器VERILOG,用于学习FPGA，编译已通过-VERILOG 计数器
(系统自动生成,下载前可以参看下载内容)
下载文件列表
count4\ciunt4.cr.mti
......\ciunt4.v.bak
......\count.cr.mti
......\count4.asm.rpt
......\count4.cr.mti
......\count4.done
......\count4.eda.rpt
......\count4.fit.rpt
......\count4.fit.smsg
......\count4.fit.summary
......\count4.flow.rpt
......\count4.map.rpt
......\count4.map.summary
......\count4.pin
......\count4.pof
......\count4.qpf
......\count4.qsf
......\count4.qws
......\count4.tan.rpt
......\count4.tan.summary
......\count4.v
......\count4.v.bak
......\count4_v.sdo
......\countp.v
......\countp.v.bak
......\db\count4.asm.qmsg
......\..\count4.asm_labs.ddb
......\..\count4.cbx.xml
......\..\count4.cmp.cdb
......\..\count4.cmp.hdb
......\..\count4.cmp.logdb
......\..\count4.cmp.rdb
......\..\count4.cmp.tdb
......\..\count4.cmp0.ddb
......\..\count4.dbp
......\..\count4.db_info
......\..\count4.eco.cdb
......\..\count4.eda.qmsg
......\..\count4.fit.qmsg
......\..\count4.hier_info
......\..\count4.hif
......\..\count4.map.cdb
......\..\count4.map.hdb
......\..\count4.map.logdb
......\..\count4.map.qmsg
......\..\count4.pre_map.cdb
......\..\count4.pre_map.hdb
......\..\count4.psp
......\..\count4.pss
......\..\count4.rtlv.hdb
......\..\count4.rtlv_sg.cdb
......\..\count4.rtlv_sg_swap.cdb
......\..\count4.sgdiff.cdb
......\..\count4.sgdiff.hdb
......\..\count4.signalprobe.cdb
......\..\count4.sld_design_entry.sci
......\..\count4.sld_design_entry_dsc.sci
......\..\count4.syn_hier_info
......\..\count4.tan.qmsg
......\..\count4.tis_db_list.ddb
......\..\prev_cmp_count4.asm.qmsg
......\..\prev_cmp_count4.eda.qmsg
......\..\prev_cmp_count4.fit.qmsg
......\..\prev_cmp_count4.map.qmsg
......\..\prev_cmp_count4.qmsg
......\..\prev_cmp_count4.tan.qmsg
......\newcount4.cr.mti
......\newcount4.mpf
......\simulation\modelsim\count4.vo
......\..........\........\count4_modelsim.xrf
......\..........\........\count4_v.sdo
......\..........\........\countp.v
......\..........\........\maxii_atoms.v
......\transcript
......\vish_stacktrace.vstf
......\vsim.wlf
......\work\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\verilog.asm
......\....\............................\_primary.dat
......\....\............................\_primary.vhd
......\....\count4\verilog.asm
......\....\......\_primary.dat
......\....\......\_primary.vhd
......\....\.....p\verilog.asm
......\....\......\_primary.dat
......\....\......\_primary.vhd
......\....\maxii_and1\verilog.asm
......\....\..........\_primary.dat
......\....\..........\_primary.vhd
......\....\..........6\verilog.asm
......\....\...........\_primary.dat
......\....\...........\_primary.vhd
......\....\.......synch_lcell\verilog.asm
......\....\..................\_primary.dat
......\....\..................\_primary.vhd
......\....\......b17mux21\verilog.asm
......\....\..............\_primary.dat
......\....\..............\_primary.vhd
......\....\.......5mux21\verilog.asm
......\....\.............\_primary.dat
......\....\.............\_primary.vhd