文件名称:8-bit-RISC_CPU
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8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
0_modelsim
..........\sourcecode
..........\..........\accum.v
..........\..........\addr_decode.v
..........\..........\adr.v
..........\..........\alu.v
..........\..........\clk_gen.v
..........\..........\counter.v
..........\..........\cpu.v
..........\..........\cputop.v
..........\..........\datactl.v
..........\..........\machine.v
..........\..........\machinectl.v
..........\..........\ram.v
..........\..........\readme.txt
..........\..........\register.v
..........\..........\rom.v
..........\..........\testcode
..........\..........\........\test1.dat
..........\..........\........\test1.pro
..........\..........\........\test2.dat
..........\..........\........\test2.pro
..........\..........\........\test3.dat
..........\..........\........\test3.pro
..........\test1.dat
..........\test1.pro
..........\test2.dat
..........\test2.pro
..........\test3.dat
..........\test3.pro
..........\vsim.wlf
..........\work
..........\....\@_opt
..........\....\.....\_deps
..........\....\.....\vopt0s06h6
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..........\....\.....\voptkaqabb
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..........\....\.....\voptxdym0y
..........\....\.....\vopty4c2di
..........\....\.....\voptyakgv0
..........\....\.....\voptyi3tfa
..........\....\@_opt1
..........\....\......\_deps
..........\....\......\vopt0m5mzc