文件名称:zhuangtai
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Verilog语言实现状态机的设计，实现的状态机总共有三种，均给出了具体的实现方案-Design and implementation of the state machine of the Verilog language, the state machine to achieve a total of three, were given a concrete implementation scheme
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下载文件列表
zhuangtai\db\logic_util_heursitic.dat
.........\..\prev_cmp_zhuangtai.qmsg
.........\..\zhuangtai.amm.cdb
.........\..\zhuangtai.asm.qmsg
.........\..\zhuangtai.asm.rdb
.........\..\zhuangtai.asm_labs.ddb
.........\..\zhuangtai.atom.rvd
.........\..\zhuangtai.atom_map.rvd
.........\..\zhuangtai.cbx.xml
.........\..\zhuangtai.cmp.bpm
.........\..\zhuangtai.cmp.cdb
.........\..\zhuangtai.cmp.hdb
.........\..\zhuangtai.cmp.kpt
.........\..\zhuangtai.cmp.logdb
.........\..\zhuangtai.cmp.rdb
.........\..\zhuangtai.cmp0.ddb
.........\..\zhuangtai.cmp1.ddb
.........\..\zhuangtai.cmp2.ddb
.........\..\zhuangtai.cmp_merge.kpt
.........\..\zhuangtai.db_info
.........\..\zhuangtai.eda.qmsg
.........\..\zhuangtai.fit.qmsg
.........\..\zhuangtai.hier_info
.........\..\zhuangtai.hif
.........\..\zhuangtai.idb.cdb
.........\..\zhuangtai.lpc.html
.........\..\zhuangtai.lpc.rdb
.........\..\zhuangtai.lpc.txt
.........\..\zhuangtai.map.bpm
.........\..\zhuangtai.map.cdb
.........\..\zhuangtai.map.hdb
.........\..\zhuangtai.map.kpt
.........\..\zhuangtai.map.logdb
.........\..\zhuangtai.map.qmsg
.........\..\zhuangtai.map_bb.cdb
.........\..\zhuangtai.map_bb.hdb
.........\..\zhuangtai.map_bb.logdb
.........\..\zhuangtai.pre_map.cdb
.........\..\zhuangtai.pre_map.hdb
.........\..\zhuangtai.rpp.qmsg
.........\..\zhuangtai.rtlv.hdb
.........\..\zhuangtai.rtlv_sg.cdb
.........\..\zhuangtai.rtlv_sg_swap.cdb
.........\..\zhuangtai.sgate.rvd
.........\..\zhuangtai.sgate_sm.rvd
.........\..\zhuangtai.sgdiff.cdb
.........\..\zhuangtai.sgdiff.hdb
.........\..\zhuangtai.sld_design_entry.sci
.........\..\zhuangtai.sld_design_entry_dsc.sci
.........\..\zhuangtai.smart_action.txt
.........\..\zhuangtai.sta.qmsg
.........\..\zhuangtai.sta.rdb
.........\..\zhuangtai.sta_cmp.8_slow.tdb
.........\..\zhuangtai.syn_hier_info
.........\..\zhuangtai.tis_db_list.ddb
.........\..\zhuangtai.tmw_info
.........\incremental_db\compiled_partitions\zhuangtai.db_info
.........\..............\...................\zhuangtai.root_partition.cmp.cdb
.........\..............\...................\zhuangtai.root_partition.cmp.dfp
.........\..............\...................\zhuangtai.root_partition.cmp.hdb
.........\..............\...................\zhuangtai.root_partition.cmp.kpt
.........\..............\...................\zhuangtai.root_partition.cmp.logdb
.........\..............\...................\zhuangtai.root_partition.cmp.rcfdb
.........\..............\...................\zhuangtai.root_partition.map.cdb
.........\..............\...................\zhuangtai.root_partition.map.dpi
.........\..............\...................\zhuangtai.root_partition.map.hbdb.cdb
.........\..............\...................\zhuangtai.root_partition.map.hbdb.hb_info
.........\..............\...................\zhuangtai.root_partition.map.hbdb.hdb
.........\..............\...................\zhuangtai.root_partition.map.hbdb.sig
.........\..............\...................\zhuangtai.root_partition.map.hdb
.........\..............\...................\zhuangtai.root_partition.map.kpt
.........\..............\README
.........\simulation\modelsim\modelsim.ini
.........\..........\........\msim_transcript
.........\..........\........\rtl_work\zhuangtai\verilog.prw
.........\..........\........\........\.........\verilog.psm
.........\..........\........\........\.........\_primary.dat
.........\..........\........\........\.........\_primary.dbs
.........\..........\........\........\.........\_primary.vhd
.........\..........\........\........\........._vlg_tst\verilog.prw
.........\..........\........\........\.................\verilog.psm
.........\..........\........\........\.................\_primary.dat
.........\..........\........\........\.................\_primary.dbs
.........\..........\........\........\.................\_primary.vhd
.........\..........\........\........\_info
.........\..........\........\........\_vmake
.........\..........\........\vsim.wlf
.........\..........\........\zhuangtai.sft
.........\..........\........\zhuangtai.vo
.........\..........\.....