文件名称:verilogvga256

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2014-03-27
  • 文件大小:
  • 411kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • t***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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在Quartus II编译环境下的,VGA256色源代码,显示效果是10x10的像素块在移动。-In the Quartus II compiler environment, VGA256 color source code, display a 10x10 pixel blocks on the move.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





verilogvga256\db\.cmp.kpt

.............\..\logic_util_heursitic.dat

.............\..\prev_cmp_vga_dis.asm.qmsg

.............\..\prev_cmp_vga_dis.fit.qmsg

.............\..\prev_cmp_vga_dis.map.qmsg

.............\..\prev_cmp_vga_dis.qmsg

.............\..\prev_cmp_vga_dis.tan.qmsg

.............\..\vga_dis.asm.qmsg

.............\..\vga_dis.asm.rdb

.............\..\vga_dis.asm_labs.ddb

.............\..\vga_dis.cbx.xml

.............\..\vga_dis.cmp.cdb

.............\..\vga_dis.cmp.hdb

.............\..\vga_dis.cmp.idb

.............\..\vga_dis.cmp.kpt

.............\..\vga_dis.cmp.logdb

.............\..\vga_dis.cmp.rdb

.............\..\vga_dis.cmp0.ddb

.............\..\vga_dis.db_info

.............\..\vga_dis.eda.qmsg

.............\..\vga_dis.fit.qmsg

.............\..\vga_dis.hier_info

.............\..\vga_dis.hif

.............\..\vga_dis.ipinfo

.............\..\vga_dis.lpc.html

.............\..\vga_dis.lpc.rdb

.............\..\vga_dis.lpc.txt

.............\..\vga_dis.map.cdb

.............\..\vga_dis.map.hdb

.............\..\vga_dis.map.logdb

.............\..\vga_dis.map.qmsg

.............\..\vga_dis.map.rdb

.............\..\vga_dis.pre_map.hdb

.............\..\vga_dis.pti_db_list.ddb

.............\..\vga_dis.root_partition.map.reg_db.cdb

.............\..\vga_dis.routing.rdb

.............\..\vga_dis.rtlv.hdb

.............\..\vga_dis.rtlv_sg.cdb

.............\..\vga_dis.rtlv_sg_swap.cdb

.............\..\vga_dis.sgdiff.cdb

.............\..\vga_dis.sgdiff.hdb

.............\..\vga_dis.sld_design_entry.sci

.............\..\vga_dis.sld_design_entry_dsc.sci

.............\..\vga_dis.smart_action.txt

.............\..\vga_dis.sta.qmsg

.............\..\vga_dis.sta.rdb

.............\..\vga_dis.sta_cmp.5_slow.tdb

.............\..\vga_dis.syn_hier_info

.............\..\vga_dis.tis_db_list.ddb

.............\..\vga_dis.tmw_info

.............\..\vga_dis.vpr.ammdb

.............\..\vga_dis_global_asgn_op.abo

.............\incremental_db\compiled_partitions\vga_dis.db_info

.............\..............\...................\vga_dis.root_partition.map.kpt

.............\..............\README

.............\simulation\modelsim\modelsim.ini

.............\..........\........\msim_transcript

.............\..........\........\rtl_work\vga_dis\verilog.prw

.............\..........\........\........\.......\verilog.psm

.............\..........\........\........\.......\_primary.dat

.............\..........\........\........\.......\_primary.dbs

.............\..........\........\........\.......\_primary.vhd

.............\..........\........\........\_info

.............\..........\........\........\_vmake

.............\..........\........\vga_dis.sft

.............\..........\........\vga_dis.vo

.............\..........\........\vga_dis_modelsim.xrf

.............\..........\........\vga_dis_run_msim_rtl_verilog.do

.............\..........\........\vga_dis_v.sdo

.............\vga_dis.asm.rpt

.............\vga_dis.cdf

.............\vga_dis.done

.............\vga_dis.eda.rpt

.............\vga_dis.fit.rpt

.............\vga_dis.fit.smsg

.............\vga_dis.fit.summary

.............\vga_dis.flow.rpt

.............\vga_dis.jdi

.............\vga_dis.map.rpt

.............\vga_dis.map.summary

.............\vga_dis.pin

.............\vga_dis.pof

.............\vga_dis.qpf

.............\vga_dis.qsf

.............\vga_dis.qws

.............\vga_dis.sta.rpt

.............\vga_dis.sta.summary

.............\vga_dis.tan.rpt

.............\vga_dis.tan.summary

.............\vga_dis.v

.............\vga_dis.v.bak

.............\vga_dis_assignment_defaults.qdf

.............\vga_dis_nativelink_simulation.rpt

.............\simulation\modelsim\rtl_work\vga_dis

.............\..........\........\........\_temp

.............\..........\........\rtl_work

.............\incremental_db\compiled_partitions

.............\simulation\modelsim

.............\db

.............\incremental_db

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