文件名称:MIPS-CPU
介绍说明--下载内容均来自于网络,请自行研究使用
完整的32位MIPS处理器工程,拥有整个工程和doc文件说明-Full 32-bit MIPS processor works with the entire project and doc file descr iption
(系统自动生成,下载前可以参看下载内容)
下载文件列表
一个完整的MIPS CPU\MIPS\ISE\.untf
..................\....\...\automake.log
..................\....\...\global.xpi
..................\....\...\global_map.ncd
..................\....\...\global_map.ngm
..................\....\...\global_pad.csv
..................\....\...\global_pad.txt
..................\....\...\global_vhdl.prj
..................\....\...\ISE.dhp
..................\....\...\ISE.npl
..................\....\...\main.bld
..................\....\...\main.cmd_log
..................\....\...\main.lso
..................\....\...\main.mrp
..................\....\...\main.nc1
..................\....\...\main.ncd
..................\....\...\main.ngc
..................\....\...\main.ngd
..................\....\...\main.ngm
..................\....\...\main.ngr
..................\....\...\main.pad
..................\....\...\main.pad_txt
..................\....\...\main.par
..................\....\...\main.par_nlf
..................\....\...\main.pcf
..................\....\...\main.placed_ncd_tracker
..................\....\...\main.prj
..................\....\...\main.routed_ncd_tracker
..................\....\...\main.stx
..................\....\...\main.syr
..................\....\...\main.twr
..................\....\...\main.twx
..................\....\...\main.versim_par
..................\....\...\main.xpi
..................\....\...\main_map.ncd
..................\....\...\main_map.ngm
..................\....\...\main_pad.csv
..................\....\...\main_pad.txt
..................\....\...\main_TEST_v_tf.tdo
..................\....\...\main_TEST_v_tf.udo
..................\....\...\main_timesim.nlf
..................\....\...\main_timesim.sdf
..................\....\...\main_timesim.v
..................\....\...\main_vhdl.prj
..................\....\...\TEST.v
..................\....\...\transcript
..................\....\...\vsim.wlf
..................\....\...\work\_info
..................\....\...\xst\work\hdllib.ref
..................\....\...\...\....\vlg0A\Data_Memory.bin
..................\....\...\...\....\...15\global.bin
..................\....\...\...\....\...20\Registers.bin
..................\....\...\...\....\....D\main.bin
..................\....\...\...\....\...30\Decode.bin
..................\....\...\...\....\....B\Code_Memory.bin
..................\....\...\...\....\...41\Control.bin
..................\....\...\...\....\....7\Execute.bin
..................\....\...\...\....\...62\Fetch.bin
..................\....\...\_ngo\netlist.lst
..................\....\...\._projnav\coregen.rsp
..................\....\...\.........\createTF.err
..................\....\...\.........\ednTOngd_tcl.rsp
..................\....\...\.........\global.xst
..................\....\...\.........\ISE.gfl
..................\....\...\.........\ISE_flowplus.gfl
..................\....\...\.........\main.xst
..................\....\...\.........\map.log
..................\....\...\.........\nc1TOncd_tcl.rsp
..................\....\...\.........\netgen_par_tcl.rsp
..................\....\...\.........\par.log
..................\....\...\.........\posttrc.log
..................\....\...\.........\runXst_tcl.rsp
..................\....\...\__projnav.log
..................\....\mips.doc
..................\....\ModelSim\MIPS.cr.mti
..................\....\........\MIPS.mpf
..................\....\........\work\@code_@memory\verilog.asm
..................\....\........\....\.............\_primary.dat
..................\....\........\....\.............\_primary.vhd
..................\....\........\....\...ntrol\verilog.asm
..................\....\........\....\........\_primary.dat
..................\....\........\....\........\_primary.vhd
..................\....\........\....\.data_@memory\verilog.asm
..................\....\........\....\.............\_primary.dat
..................\....\........\....\.............\_primary.vhd
..................\....\........\....\..ecode\verilog.asm
..................\....\........\....\.......\_primary.dat
..................\....\........\....\.......\_primary.vhd
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