文件名称:t1_comm
介绍说明－－下载内容均来自于网络，请自行研究使用
该程序包括数据的发送，加密，奇偶校验，接收，解密等模块，实现了一个完整的收发操作。为了测试方便，我们将接收到的数据直接引入发送端口，为此，我们编写了测试脚本文件，验证程序的正确性。该程序模块较多，读者可参考压缩包内的原理框图文件，以便于理解。-The program includes sending, encryption, parity, receive, decrypt data modules to achieve a complete transceiver operation. In order to facilitate the testing, we will receive the data sent directly introduced into the port, and we write the test scr ipt file, verify the correctness of the program. The program modules are more compressed block diagram of the reader is referred to within the document, in order to understand.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
t1_comm\altpll0.bsf
.......\altpll0.ppf
.......\altpll0.qip
.......\altpll0.v
.......\altpll0_bb.v
.......\db\logic_util_heursitic.dat
.......\..\prev_cmp_t1_comm.qmsg
.......\..\t1_comm.cbx.xml
.......\..\t1_comm.cmp.rdb
.......\..\t1_comm.cmp_merge.kpt
.......\..\t1_comm.db_info
.......\..\t1_comm.hier_info
.......\..\t1_comm.hif
.......\..\t1_comm.lpc.html
.......\..\t1_comm.lpc.rdb
.......\..\t1_comm.lpc.txt
.......\..\t1_comm.map.bpm
.......\..\t1_comm.map.cdb
.......\..\t1_comm.map.hdb
.......\..\t1_comm.map.kpt
.......\..\t1_comm.map.logdb
.......\..\t1_comm.map.qmsg
.......\..\t1_comm.map.rdb
.......\..\t1_comm.map_bb.cdb
.......\..\t1_comm.map_bb.hdb
.......\..\t1_comm.map_bb.logdb
.......\..\t1_comm.pre_map.cdb
.......\..\t1_comm.pre_map.hdb
.......\..\t1_comm.root_partition.map.reg_db.cdb
.......\..\t1_comm.rtlv.hdb
.......\..\t1_comm.rtlv_sg.cdb
.......\..\t1_comm.rtlv_sg_swap.cdb
.......\..\t1_comm.sgdiff.cdb
.......\..\t1_comm.sgdiff.hdb
.......\..\t1_comm.sld_design_entry.sci
.......\..\t1_comm.sld_design_entry_dsc.sci
.......\..\t1_comm.smart_action.txt
.......\..\t1_comm.smp_dump.txt
.......\..\t1_comm.syn_hier_info
.......\..\t1_comm.tis_db_list.ddb
.......\..\t1_comm.tmw_info
.......\des.bsf
.......\des.v
.......\des.v.bak
.......\greybox_tmp\cbx_args.txt
.......\incremental_db\compiled_partitions\t1_comm.db_info
.......\..............\...................\t1_comm.root_partition.map.cdb
.......\..............\...................\t1_comm.root_partition.map.dpi
.......\..............\...................\t1_comm.root_partition.map.hbdb.cdb
.......\..............\...................\t1_comm.root_partition.map.hbdb.hb_info
.......\..............\...................\t1_comm.root_partition.map.hbdb.hdb
.......\..............\...................\t1_comm.root_partition.map.hbdb.sig
.......\..............\...................\t1_comm.root_partition.map.hdb
.......\..............\...................\t1_comm.root_partition.map.kpt
.......\..............\README
.......\manchester_decoder.bsf
.......\manchester_decoder.v
.......\manchester_decoder.v.bak
.......\manchester_encoder.bsf
.......\manchester_encoder.v
.......\manchester_encoder.v.bak
.......\parity_check.bsf
.......\parity_check.v
.......\parity_check.v.bak
.......\parity_sender.bsf
.......\parity_sender.v
.......\parity_sender.v.bak
.......\parity_sender_tb.v
.......\parity_sender_tb.v.bak
.......\receriver_inteface.bsf
.......\receriver_inteface.v
.......\receriver_inteface.v.bak
.......\sender_inteface.bsf
.......\sender_inteface.v
.......\sender_inteface.v.bak
.......\ser.bsf
.......\ser.v
.......\ser.v.bak
.......\ser_tb.v
.......\ser_tb.v.bak
.......\.imulation\modelsim\modelsim.ini
.......\..........\........\msim_transcript
.......\..........\........\rtl_work\altpll0\verilog.prw
.......\..........\........\........\.......\verilog.psm
.......\..........\........\........\.......\_primary.dat
.......\..........\........\........\.......\_primary.dbs
.......\..........\........\........\.......\_primary.vhd
.......\..........\........\........\des\verilog.prw
.......\..........\........\........\...\verilog.psm
.......\..........\........\........\...\_primary.dat
.......\..........\........\........\...\_primary.dbs
.......\..........\........\........\...\_primary.vhd
.......\..........\........\........\manchester_decoder\verilog.prw
.......\..........\........\........\..................\verilog.psm
.......\..........\........\........\..................\_primary.dat
.......\..........\........\........\..................\_primary.dbs
.......\..........\........\........\..................\_primary.vhd
.......\..........\........\........\...........encoder\verilog.prw
.......\..........\........\........\..................\verilog.psm
.......\..........\........\........\..................\_primary.dat