文件名称:t4_fifo
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FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want to be useful.
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下载文件列表
t4_fifo\db\altsyncram_8sj1.tdf
.......\..\altsyncram_amc1.tdf
.......\..\altsyncram_oog1.tdf
.......\..\a_dpfifo_gj31.tdf
.......\..\a_fefifo_08f.tdf
.......\..\cntr_hjb.tdf
.......\..\cntr_tj7.tdf
.......\..\dpram_0u01.tdf
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_t4_fifo.qmsg
.......\..\scfifo_9d31.tdf
.......\..\t4_fifo.cbx.xml
.......\..\t4_fifo.cmp.rdb
.......\..\t4_fifo.cmp_merge.kpt
.......\..\t4_fifo.db_info
.......\..\t4_fifo.hier_info
.......\..\t4_fifo.hif
.......\..\t4_fifo.lpc.html
.......\..\t4_fifo.lpc.rdb
.......\..\t4_fifo.lpc.txt
.......\..\t4_fifo.map.bpm
.......\..\t4_fifo.map.cdb
.......\..\t4_fifo.map.hdb
.......\..\t4_fifo.map.kpt
.......\..\t4_fifo.map.logdb
.......\..\t4_fifo.map.qmsg
.......\..\t4_fifo.map.rdb
.......\..\t4_fifo.map_bb.cdb
.......\..\t4_fifo.map_bb.hdb
.......\..\t4_fifo.map_bb.logdb
.......\..\t4_fifo.pre_map.cdb
.......\..\t4_fifo.pre_map.hdb
.......\..\t4_fifo.root_partition.map.reg_db.cdb
.......\..\t4_fifo.rtlv.hdb
.......\..\t4_fifo.rtlv_sg.cdb
.......\..\t4_fifo.rtlv_sg_swap.cdb
.......\..\t4_fifo.sgdiff.cdb
.......\..\t4_fifo.sgdiff.hdb
.......\..\t4_fifo.sld_design_entry.sci
.......\..\t4_fifo.sld_design_entry_dsc.sci
.......\..\t4_fifo.smart_action.txt
.......\..\t4_fifo.syn_hier_info
.......\..\t4_fifo.tis_db_list.ddb
.......\fifo_verilog.bsf
.......\fifo_verilog.v
.......\fifo_verilog.v.bak
.......\fifo_verilog_tb.v
.......\fifo_verilog_tb.v.bak
.......\greybox_tmp\cbx_args.txt
.......\incremental_db\compiled_partitions\t4_fifo.db_info
.......\..............\...................\t4_fifo.root_partition.map.cdb
.......\..............\...................\t4_fifo.root_partition.map.dpi
.......\..............\...................\t4_fifo.root_partition.map.hbdb.cdb
.......\..............\...................\t4_fifo.root_partition.map.hbdb.hb_info
.......\..............\...................\t4_fifo.root_partition.map.hbdb.hdb
.......\..............\...................\t4_fifo.root_partition.map.hbdb.sig
.......\..............\...................\t4_fifo.root_partition.map.hdb
.......\..............\...................\t4_fifo.root_partition.map.kpt
.......\..............\README
.......\my_fifo.bsf
.......\my_fifo.cmp
.......\my_fifo.qip
.......\my_fifo.vhd
.......\my_fifo_tb.vhd
.......\my_fifo_tb.vhd.bak
.......\simulation\modelsim\modelsim.ini
.......\..........\........\msim_transcript
.......\..........\........\rtl_work\fifo_verilog\verilog.prw
.......\..........\........\........\............\verilog.psm
.......\..........\........\........\............\_primary.dat
.......\..........\........\........\............\_primary.dbs
.......\..........\........\........\............\_primary.vhd
.......\..........\........\........\............_tb\verilog.prw
.......\..........\........\........\...............\verilog.psm
.......\..........\........\........\...............\_primary.dat
.......\..........\........\........\...............\_primary.dbs
.......\..........\........\........\...............\_primary.vhd
.......\..........\........\........\_info
.......\..........\........\........\_vmake
.......\..........\........\t4_fifo_run_msim_rtl_verilog.do
.......\..........\........\t4_fifo_run_msim_rtl_verilog.do.bak
.......\..........\........\t4_fifo_run_msim_rtl_vhdl.do
.......\..........\........\t4_fifo_run_msim_rtl_vhdl.do.bak
.......\..........\........\vsim.wlf
.......\t4_fifo.bdf
.......\t4_fifo.done
.......\t4_fifo.flow.rpt
.......\t4_fifo.map.rpt
.......\t4_fifo.map.summary
.......\t4_fifo.qpf
.......\t4_fifo.qsf
.......\t4_fifo.qws
.......\t4_fifo_assignment_defaults.qdf
.......\t4_fifo_nativelink_simulation.rpt
.......\simulation\modelsim\rtl_work\fifo_verilog
.......\..........\........\........\fifo_verilog_tb
.......\..........\........\........\_temp
.......\..........\........\rtl_work
.......\incremental_db\compiled_partitions
.......\simulation\modelsim