文件名称:mux16
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基于FPGA的verilog编写的乘法器-FPGA-based multiplier verilog prepared
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下载文件列表
mux16
.....\db
.....\..\logic_util_heursitic.dat
.....\..\mux16.db_info
.....\..\mux16.eco.cdb
.....\..\mux16.sim.cvwf
.....\..\mux16.sld_design_entry.sci
.....\..\mux16_global_asgn_op.abo
.....\..\prev_cmp_mux16.asm.qmsg
.....\..\prev_cmp_mux16.eda.qmsg
.....\..\prev_cmp_mux16.fit.qmsg
.....\..\prev_cmp_mux16.map.qmsg
.....\..\prev_cmp_mux16.qmsg
.....\..\prev_cmp_mux16.tan.qmsg
.....\..\wed.wsf
.....\incremental_db
.....\..............\README
.....\..............\compiled_partitions
.....\..............\...................\mux16.root_partition.map.kpt
.....\mux16.asm.rpt
.....\mux16.done
.....\mux16.eda.rpt
.....\mux16.fit.rpt
.....\mux16.fit.smsg
.....\mux16.fit.summary
.....\mux16.flow.rpt
.....\mux16.map.rpt
.....\mux16.map.smsg
.....\mux16.map.summary
.....\mux16.pin
.....\mux16.pof
.....\mux16.qpf
.....\mux16.qsf
.....\mux16.sim.rpt
.....\mux16.tan.rpt
.....\mux16.tan.summary
.....\mux16.v
.....\mux16.v.bak
.....\mux16.vwf
.....\mux16_assignment_defaults.qdf
.....\mux16_nativelink_simulation.rpt
.....\simulation
.....\..........\modelsim
.....\..........\........\maxii_atoms.v
.....\..........\........\modelsim.ini
.....\..........\........\msim_transcript
.....\..........\........\mux16.sft
.....\..........\........\mux16.vo
.....\..........\........\mux16_modelsim.xrf
.....\..........\........\mux16_run_msim_rtl_verilog.do
.....\..........\........\mux16_v.sdo
.....\..........\........\rtl_work
.....\..........\........\........\_info
.....\..........\........\........\_temp
.....\..........\........\........\_vmake
.....\..........\........\........\mux16
.....\..........\........\........\.....\_primary.dat
.....\..........\........\........\.....\_primary.dbs
.....\..........\........\........\.....\_primary.vhd
.....\..........\........\........\.....\verilog.prw
.....\..........\........\........\.....\verilog.psm
.....\..........\........\vtf_test.v