文件名称:fenpin
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这个是简单的ppga的verilog的实例。入门着可以看看。-This is an example of a simple ppga of verilog. Getting a look at.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fenpin\db\half_clk.cbx.xml
......\..\half_clk.cmp.hdb
......\..\half_clk.cmp.rdb
......\..\half_clk.cmp_merge.kpt
......\..\half_clk.db_info
......\..\half_clk.eda.qmsg
......\..\half_clk.hier_info
......\..\half_clk.hif
......\..\half_clk.lpc.html
......\..\half_clk.lpc.rdb
......\..\half_clk.lpc.txt
......\..\half_clk.map.bpm
......\..\half_clk.map.cdb
......\..\half_clk.map.hdb
......\..\half_clk.map.kpt
......\..\half_clk.map.logdb
......\..\half_clk.map.qmsg
......\..\half_clk.map_bb.cdb
......\..\half_clk.map_bb.hdb
......\..\half_clk.map_bb.logdb
......\..\half_clk.pre_map.cdb
......\..\half_clk.pre_map.hdb
......\..\half_clk.rtlv.hdb
......\..\half_clk.rtlv_sg.cdb
......\..\half_clk.rtlv_sg_swap.cdb
......\..\half_clk.sgdiff.cdb
......\..\half_clk.sgdiff.hdb
......\..\half_clk.sld_design_entry.sci
......\..\half_clk.sld_design_entry_dsc.sci
......\..\half_clk.smart_action.txt
......\..\half_clk.syn_hier_info
......\..\half_clk.tis_db_list.ddb
......\..\logic_util_heursitic.dat
......\..\prev_cmp_half_clk.qmsg
......\half_clk.bsf
......\half_clk.done
......\half_clk.eda.rpt
......\half_clk.flow.rpt
......\half_clk.map.rpt
......\half_clk.map.summary
......\half_clk.qpf
......\half_clk.qsf
......\half_clk.v
......\half_clk.v.bak
......\half_clk_nativelink_simulation.rpt
......\incremental_db\compiled_partitions\half_clk.db_info
......\..............\...................\half_clk.root_partition.map.cdb
......\..............\...................\half_clk.root_partition.map.dpi
......\..............\...................\half_clk.root_partition.map.hbdb.cdb
......\..............\...................\half_clk.root_partition.map.hbdb.hb_info
......\..............\...................\half_clk.root_partition.map.hbdb.hdb
......\..............\...................\half_clk.root_partition.map.hbdb.sig
......\..............\...................\half_clk.root_partition.map.hdb
......\..............\...................\half_clk.root_partition.map.kpt
......\..............\README
......\simulation\modelsim\half_clk.vt
......\..........\........\half_clk.vt.bak
......\..........\........\half_clk_run_msim_rtl_verilog.do
......\..........\........\modelsim.ini
......\..........\........\msim_transcript
......\..........\........\rtl_work\half_clk\verilog.prw
......\..........\........\........\........\verilog.psm
......\..........\........\........\........\_primary.dat
......\..........\........\........\........\_primary.dbs
......\..........\........\........\........\_primary.vhd
......\..........\........\........\........_vlg_tst\verilog.prw
......\..........\........\........\................\verilog.psm
......\..........\........\........\................\_primary.dat
......\..........\........\........\................\_primary.dbs
......\..........\........\........\................\_primary.vhd
......\..........\........\........\_info
......\..........\........\........\_vmake
......\..........\........\vsim.wlf
......\..........\........\rtl_work\half_clk
......\..........\........\........\half_clk_vlg_tst
......\..........\........\........\_temp
......\..........\........\rtl_work
......\incremental_db\compiled_partitions
......\simulation\modelsim
......\db
......\incremental_db
......\simulation
fenpin