文件名称:sw_seg_test
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拨码开关输入数码管显示实验，用于FPGA开发板-DIP switch input digital display experiment for FPGA development board
(系统自动生成,下载前可以参看下载内容)
下载文件列表
基础实验05-拨码开关输入数码管显示实验\sw_seg_test\bitgen.ut
.....................................\...........\sw_seg_test.dhp
.....................................\...........\sw_seg_test.ise
.....................................\...........\sw_seg_test.ise_ISE_Backup
.....................................\...........\topdesign.bgn
.....................................\...........\topdesign.bit
.....................................\...........\topdesign.bld
.....................................\...........\topdesign.cmd_log
.....................................\...........\topdesign.drc
.....................................\...........\topdesign.lso
.....................................\...........\topdesign.mrp
.....................................\...........\topdesign.nc1
.....................................\...........\topdesign.ncd
.....................................\...........\topdesign.ngc
.....................................\...........\topdesign.ngd
.....................................\...........\topdesign.ngm
.....................................\...........\topdesign.ngr
.....................................\...........\topdesign.pad
.....................................\...........\topdesign.pad_txt
.....................................\...........\topdesign.par
.....................................\...........\topdesign.pcf
.....................................\...........\topdesign.placed_ncd_tracker
.....................................\...........\topdesign.prj
.....................................\...........\topdesign.routed_ncd_tracker
.....................................\...........\topdesign.stx
.....................................\...........\topdesign.syr
.....................................\...........\topdesign.twr
.....................................\...........\topdesign.twx
.....................................\...........\topdesign.ucf
.....................................\...........\topdesign.ucf.untf
.....................................\...........\topdesign.ut
.....................................\...........\topdesign.vhd
.....................................\...........\topdesign.xpi
.....................................\...........\topdesign_map.ncd
.....................................\...........\topdesign_map.ngm
.....................................\...........\topdesign_pad.csv
.....................................\...........\topdesign_pad.txt
.....................................\...........\topdesign_summary.html
.....................................\...........\_impact.cmd
.....................................\...........\._projnav\bitgen.rsp
.....................................\...........\.........\ednTOngd_tcl.rsp
.....................................\...........\.........\nc1TOncd_tcl.rsp
.....................................\...........\.........\runXst_tcl.rsp
.....................................\...........\.........\sumrpt_tcl.rsp
.....................................\...........\.........\sw_seg_test.gfl
.....................................\...........\.........\sw_seg_test_flowplus.gfl
.....................................\...........\.........\topdesign.xst
.....................................\...........\.........\topdesign_ncdTOut_tcl.rsp
.....................................\...........\.ngo\netlist.lst
.....................................\...........\xst\work\hdllib.ref
.....................................\...........\...\....\hdpdeps.ref
.....................................\...........\...\....\sub00\vhpl00.vho
.....................................\...........\...\....\.....\vhpl01.vho
.....................................\...........\...\dump.xst\topdesign.prj\ngx\opt
.....................................\...........\...\........\.............\...\notopt
.....................................\...........\...\........\.............\ngx
.....................................\...........\...\work\sub00
.....................................\...........\...\dump.xst\topdesign.prj
.....................................\...........\...\work
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