文件名称:digital_clock

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-12-17
  • 文件大小:
  • 3.81mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 童**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

FPGA数字时钟,基于verilogHDL-FPGA digital clock, based verilogHDL
(系统自动生成,下载前可以参看下载内容)

下载文件列表





digital_clock

.............\change.bsf

.............\change.v

.............\change.v.bak

.............\db

.............\..\add_sub_7pc.tdf

.............\..\add_sub_8pc.tdf

.............\..\alt_u_div_24f.tdf

.............\..\alt_u_div_44f.tdf

.............\..\alt_u_div_64f.tdf

.............\..\digital_clock.asm.qmsg

.............\..\digital_clock.asm.rdb

.............\..\digital_clock.asm_labs.ddb

.............\..\digital_clock.cbx.xml

.............\..\digital_clock.cmp.bpm

.............\..\digital_clock.cmp.cdb

.............\..\digital_clock.cmp.hdb

.............\..\digital_clock.cmp.idb

.............\..\digital_clock.cmp.kpt

.............\..\digital_clock.cmp.logdb

.............\..\digital_clock.cmp.rdb

.............\..\digital_clock.cmp_merge.kpt

.............\..\digital_clock.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

.............\..\digital_clock.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd

.............\..\digital_clock.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd

.............\..\digital_clock.db_info

.............\..\digital_clock.eda.qmsg

.............\..\digital_clock.fit.qmsg

.............\..\digital_clock.hier_info

.............\..\digital_clock.hif

.............\..\digital_clock.ipinfo

.............\..\digital_clock.lpc.html

.............\..\digital_clock.lpc.rdb

.............\..\digital_clock.lpc.txt

.............\..\digital_clock.map.ammdb

.............\..\digital_clock.map.bpm

.............\..\digital_clock.map.cdb

.............\..\digital_clock.map.hdb

.............\..\digital_clock.map.kpt

.............\..\digital_clock.map.logdb

.............\..\digital_clock.map.qmsg

.............\..\digital_clock.map.rdb

.............\..\digital_clock.map_bb.cdb

.............\..\digital_clock.map_bb.hdb

.............\..\digital_clock.map_bb.logdb

.............\..\digital_clock.pplq.rdb

.............\..\digital_clock.pre_map.hdb

.............\..\digital_clock.pti_db_list.ddb

.............\..\digital_clock.root_partition.map.reg_db.cdb

.............\..\digital_clock.routing.rdb

.............\..\digital_clock.rtlv.hdb

.............\..\digital_clock.rtlv_sg.cdb

.............\..\digital_clock.rtlv_sg_swap.cdb

.............\..\digital_clock.sgdiff.cdb

.............\..\digital_clock.sgdiff.hdb

.............\..\digital_clock.sld_design_entry.sci

.............\..\digital_clock.sld_design_entry_dsc.sci

.............\..\digital_clock.smart_action.txt

.............\..\digital_clock.smp_dump.txt

.............\..\digital_clock.sta.qmsg

.............\..\digital_clock.sta.rdb

.............\..\digital_clock.sta_cmp.8_slow_1200mv_85c.tdb

.............\..\digital_clock.syn_hier_info

.............\..\digital_clock.tiscmp.fastest_slow_1200mv_0c.ddb

.............\..\digital_clock.tiscmp.fastest_slow_1200mv_85c.ddb

.............\..\digital_clock.tiscmp.fast_1200mv_0c.ddb

.............\..\digital_clock.tiscmp.slow_1200mv_0c.ddb

.............\..\digital_clock.tiscmp.slow_1200mv_85c.ddb

.............\..\digital_clock.tis_db_list.ddb

.............\..\digital_clock.tmw_info

.............\..\digital_clock.vpr.ammdb

.............\..\digital_clock_qsim.cbx.xml

.............\..\digital_clock_qsim.db_info

.............\..\digital_clock_qsim.eds_overflow

.............\..\digital_clock_qsim.fnsim.cdb

.............\..\digital_clock_qsim.fnsim.hdb

.............\..\digital_clock_qsim.fnsim.qmsg

.............\..\digital_clock_qsim.hier_info

.............\..\digital_clock_qsim.lpc.html

.............\..\digital_clock_qsim.lpc.rdb

.............\..\digital_clock_qsim.lpc.txt

.............\..\digital_clock_qsim.sim.hdb

.............\..\digital_clock_qsim.sim.qmsg

.............\..\digital_clock_qsim.sim.rdb

.............\..\digital_clock_qsim.sim.vwf

.............\..\digital_clock_qsim.simfam

.............\..\digital_clock_qsim.sld_design_entry_dsc.sci

.............\..\digital_clock_qsim.smart_action.txt

.............\..\logic_util_heursitic.dat

.............\..\lpm_divide_fhm.tdf

.............\..\lpm_divide_ghm.tdf

.............\..\lpm_divide_hhm.tdf

.............\..\lpm_divide_i9m.tdf

.............\..\lpm_divide_j9m.tdf

.............\

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