文件名称:pulse_generation
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一个小的激光驱动电路，调用PLL锁相环，可以产生不同脉宽，实现占空比可调-Pulse generation, Verilog written. Though simple, but I hope you will help
(系统自动生成,下载前可以参看下载内容)
下载文件列表
pulse_generation\AD_clk.qip
................\db\logic_util_heursitic.dat
................\..\PLL_1.cbx.xml
................\..\PLL_1.cmp.rdb
................\..\PLL_1.cmp_merge.kpt
................\..\PLL_1.db_info
................\..\PLL_1.hier_info
................\..\PLL_1.hif
................\..\PLL_1.ipinfo
................\..\PLL_1.lpc.html
................\..\PLL_1.lpc.rdb
................\..\PLL_1.lpc.txt
................\..\PLL_1.map.ammdb
................\..\PLL_1.map.bpm
................\..\PLL_1.map.cdb
................\..\PLL_1.map.hdb
................\..\PLL_1.map.kpt
................\..\PLL_1.map.logdb
................\..\PLL_1.map.qmsg
................\..\PLL_1.map.rdb
................\..\PLL_1.map_bb.cdb
................\..\PLL_1.map_bb.hdb
................\..\PLL_1.map_bb.logdb
................\..\PLL_1.pre_map.hdb
................\..\PLL_1.pti_db_list.ddb
................\..\PLL_1.root_partition.map.reg_db.cdb
................\..\PLL_1.rtlv.hdb
................\..\PLL_1.rtlv_sg.cdb
................\..\PLL_1.rtlv_sg_swap.cdb
................\..\PLL_1.sgdiff.cdb
................\..\PLL_1.sgdiff.hdb
................\..\PLL_1.sld_design_entry.sci
................\..\PLL_1.sld_design_entry_dsc.sci
................\..\PLL_1.smart_action.txt
................\..\PLL_1.syn_hier_info
................\..\PLL_1.tis_db_list.ddb
................\..\PLL_1.tmw_info
................\..\pll_1_altpll.v
................\..\prev_cmp_PLL_1.qmsg
................\greybox_tmp\cbx_args.txt
................\incremental_db\compiled_partitions\PLL_1.db_info
................\..............\...................\PLL_1.root_partition.cmp.dfp
................\..............\...................\PLL_1.root_partition.cmp.kpt
................\..............\...................\PLL_1.root_partition.cmp.logdb
................\..............\...................\PLL_1.root_partition.map.cdb
................\..............\...................\PLL_1.root_partition.map.dpi
................\..............\...................\PLL_1.root_partition.map.hbdb.cdb
................\..............\...................\PLL_1.root_partition.map.hbdb.hb_info
................\..............\...................\PLL_1.root_partition.map.hbdb.hdb
................\..............\...................\PLL_1.root_partition.map.hbdb.sig
................\..............\...................\PLL_1.root_partition.map.hdb
................\..............\...................\PLL_1.root_partition.map.kpt
................\..............\README
................\modelsim.ini
................\msim_transcript
................\PLLJ_PLLSPE_INFO.txt
................\PLL_1.asm.rpt
................\pll_1.bsf
................\PLL_1.cdf
................\pll_1.cmp
................\PLL_1.done
................\PLL_1.eda.rpt
................\PLL_1.fit.rpt
................\PLL_1.fit.smsg
................\PLL_1.fit.summary
................\PLL_1.flow.rpt
................\pll_1.inc
................\PLL_1.map.rpt
................\PLL_1.map.smsg
................\PLL_1.map.summary
................\PLL_1.pin
................\PLL_1.pof
................\pll_1.ppf
................\pll_1.qip
................\PLL_1.qpf
................\PLL_1.qsf
................\PLL_1.qsf.bak
................\PLL_1.qws
................\PLL_1.sof
................\PLL_1.sta.rpt
................\PLL_1.sta.summary
................\pll_1.v
................\PLL_1_assignment_defaults.qdf
................\pll_1_bb.v
................\pll_1_inst.v
................\PLL_1_nativelink_simulation.rpt
................\PLL_1_run_msim_rtl_verilog.do
................\PLL_1_run_msim_rtl_verilog.do.bak
................\PLL_1_run_msim_rtl_verilog.do.bak1
................\PLL_1_run_msim_rtl_verilog.do.bak2
................\PLL_1_run_msim_rtl_verilog.do.bak3
................\RTL\greybox_tmp\cbx_args.txt
................\...\pll_1.qip
................\...\PLL_1.v
................\...\PLL_1.v.bak
................\rtl_work\@p@l@l_1\_primary.dat
................\........\........\_primary.dbs
................\........\........\_primary.vhd
......