testwren

........\db

........\..\altsyncram_18d2.tdf

........\..\altsyncram_oqb2.tdf

........\..\logic_util_heursitic.dat

........\..\prev_cmp_testwren.qmsg

........\..\testwren.amm.cdb

........\..\testwren.asm.qmsg

........\..\testwren.asm.rdb

........\..\testwren.asm_labs.ddb

........\..\testwren.cbx.xml

........\..\testwren.cmp.bpm

........\..\testwren.cmp.cdb

........\..\testwren.cmp.hdb

........\..\testwren.cmp.kpt

........\..\testwren.cmp.logdb

........\..\testwren.cmp.rdb

........\..\testwren.cmp_merge.kpt

........\..\testwren.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

........\..\testwren.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd

........\..\testwren.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd

........\..\testwren.db_info

........\..\testwren.eda.qmsg

........\..\testwren.fit.qmsg

........\..\testwren.hier_info

........\..\testwren.hif

........\..\testwren.idb.cdb

........\..\testwren.lpc.html

........\..\testwren.lpc.rdb

........\..\testwren.lpc.txt

........\..\testwren.map.bpm

........\..\testwren.map.cdb

........\..\testwren.map.hdb

........\..\testwren.map.kpt

........\..\testwren.map.logdb

........\..\testwren.map.qmsg

........\..\testwren.map_bb.cdb

........\..\testwren.map_bb.hdb

........\..\testwren.map_bb.logdb

........\..\testwren.pre_map.cdb

........\..\testwren.pre_map.hdb

........\..\testwren.rtlv.hdb

........\..\testwren.rtlv_sg.cdb

........\..\testwren.rtlv_sg_swap.cdb

........\..\testwren.sgdiff.cdb

........\..\testwren.sgdiff.hdb

........\..\testwren.sld_design_entry.sci

........\..\testwren.sld_design_entry_dsc.sci

........\..\testwren.smart_action.txt

........\..\testwren.sta.qmsg

........\..\testwren.sta.rdb

........\..\testwren.sta_cmp.8_slow_1200mv_85c.tdb

........\..\testwren.syn_hier_info

........\..\testwren.tiscmp.fastest_slow_1200mv_0c.ddb

........\..\testwren.tiscmp.fastest_slow_1200mv_85c.ddb

........\..\testwren.tiscmp.fast_1200mv_0c.ddb

........\..\testwren.tiscmp.slow_1200mv_0c.ddb

........\..\testwren.tiscmp.slow_1200mv_85c.ddb

........\..\testwren.tis_db_list.ddb

........\..\testwren.tmw_info

........\greybox_tmp

........\...........\cbx_args.txt

........\incremental_db

........\..............\compiled_partitions

........\..............\...................\testwren.db_info

........\..............\...................\testwren.root_partition.cmp.cdb

........\..............\...................\testwren.root_partition.cmp.dfp

........\..............\...................\testwren.root_partition.cmp.hdb

........\..............\...................\testwren.root_partition.cmp.kpt

........\..............\...................\testwren.root_partition.cmp.logdb

........\..............\...................\testwren.root_partition.cmp.rcfdb

........\..............\...................\testwren.root_partition.map.cdb

........\..............\...................\testwren.root_partition.map.dpi

........\..............\...................\testwren.root_partition.map.hbdb.cdb

........\..............\...................\testwren.root_partition.map.hbdb.hb_info

........\..............\...................\testwren.root_partition.map.hbdb.hdb

........\..............\...................\testwren.root_partition.map.hbdb.sig

........\..............\...................\testwren.root_partition.map.hdb

........\..............\...................\testwren.root_partition.map.kpt

........\..............\README

........\ram.qip

........\ram.v

........\ram_bb.v

........\simulation

........\..........\modelsim

........\..........\........\gate_work

........\..........\........\.........\testwren

........\..........\........\.........\........\verilog.prw

........\..........\........\.........\........\verilog.psm

........\..........\........\.........\........\_primary.dat

........\..........\........\.........\........\_primary.dbs

........\..........\........\.........\........\_primary.vhd

........\..........\........\.........\testwren_vlg_tst

........\..........\........\.........\................\verilog.prw

........\..........\........\.........\................\verilog.psm

........\