文件名称:verilog-source-codes
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the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog source codes\4-bit ring counter.txt
....................\decoder 4-16.txt
....................\fullsub using two half sub.txt
....................\mux 16-1.txt
....................\parallel in serial out shift register.txt
....................\priority encoder 8-3.txt
verilog source codes