文件名称:LowPowerTechniques
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Low Power Design
Nano‐scale designs at 130nm and below are now confronted with a power
dissipation level beyond the limits of IC packaging and cooling techniques
• Consequently in many designs it is not possible to increase the clock speed
when a new generation of technology is being adopted Power Wall -Low Power Design
Nano‐scale designs at 130nm and below are now confronted with a power
dissipation level beyond the limits of IC packaging and cooling techniques
• Consequently in many designs it is not possible to increase the clock speed
when a new generation of technology is being adopted Power Wall !!!
Nano‐scale designs at 130nm and below are now confronted with a power
dissipation level beyond the limits of IC packaging and cooling techniques
• Consequently in many designs it is not possible to increase the clock speed
when a new generation of technology is being adopted Power Wall -Low Power Design
Nano‐scale designs at 130nm and below are now confronted with a power
dissipation level beyond the limits of IC packaging and cooling techniques
• Consequently in many designs it is not possible to increase the clock speed
when a new generation of technology is being adopted Power Wall !!!
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LowPowerTechniques.pdf